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advance data sheet september 2001 celxpres tm t8208 atm interconnect 1 product overview 1.1 features n oc-12 data throughput on utopia (16-bit) (independently on rx and tx utopia) n shared utopia mode n utopia level 1 and 2 (8-bit/16-bit) cell-level handshake interface (atm or phy layers) n multi-phy (mphy) operation n programmable atm layer supports up to 64 phy ports n egress sdram buffer support to extend utopia output priority queues for 32k to 512k cells: 128 queues configurable up to four queues per phy with programmable sizes programmable number of utopia output queues with four levels of priority n support of atm traffic management via partial packet discard (ppd), forward explicit congestion notification (fecn), and the cell loss priority (clp) bit n programmable slew rate gtl+ i/o: programmable as bus arbiter 1.7 gbits/s cell bus operation n flexible per port cell counters n cell header insertion with virtual path identifier (vpi) and virtual channel identifier (vci) translation via external sram (up to 64k entries) n support of network node interface (nni) and user network interface (uni) header types with optional generic flow-control (gfc) insertion n optional sourcing of cell bus clocks from device n lut bypass option n tx utopia cell buffer increased to 256 cells for better queue management with sdram queue bypass option n ability for cell bus arbiter to mask devices on the cell bus n ability to modify cell bus priority based on rx phy fifo thresholds n programmable priority for control/data cells trans- mission onto cell bus n microprocessor access to all headers of control cell n ability to clear counters on read n simplified looping to any system device with a sin- gle register programming n utopia clock sourcing with additional settings n programmable operations and maintenance and resource management (oam/rm) cell routing n support of multicast and broadcast cells per phy n optional monitoring of misrouted cells n counters for dropped cells per queue n digital loopback before cell bus n microprocessor interface, supporting both motor- ola ? and intel ? modes (multiplexed and nonmulti- plexed) n control cell transmission and reception through microprocessor port n single 3.3 v power supply n 3.3 v ttl i/o (5 v tolerant) n 272-pin plastic ball grid array (pbga) package n industrial temperature range (C40 c to +85 c) n hot insertion capability n eight gpio pins n jtag support n compatible with transwitch cellbus ? 1.2 applications n asymmetric digital subscriber line (adsl) digital subscriber line access multiplexers (dslams) n access gateways n access multiplexers/concentrators n multiservice platforms
2 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 table of contents contents page 1 product overview.............................................................................................................. ..................................1 1.1 features .................................................................................................................... ................................1 1.2 applications ................................................................................................................ ...............................1 1.3 description ................................................................................................................. ...............................9 1.4 conventions ................................................................................................................. ...........................12 1.5 glossary .................................................................................................................... ..............................13 2 pinout ........................................................................................................................ ........................................14 3 powerup/reset sequence ........................................................................................................ ........................22 4 hot insertion................................................................................................................. .....................................23 5 pll configuration ............................................................................................................. ................................24 6 microprocessor interface ...................................................................................................... ............................25 6.1 microprocessor interface configuration ...................................................................................... ............25 6.2 microprocessor interrupts................................................................................................... .....................25 6.3 accessing the celxpres t8208 via microprocessor interface.................................................................25 6.3.1 accessing the extended memory registers...............................................................................26 6.3.1.1 extended memory writes.............................................................................................26 6.3.1.2 extended memory reads.............................................................................................26 6.3.2 celxpres t8208 access performance .......................................................................................27 7 general-purpose i/o (gpio) .................................................................................................... ........................28 8 look-up table ................................................................................................................. .................................29 8.1 look-up table ram........................................................................................................... .....................29 8.2 organization ................................................................................................................ ............................30 8.3 look-up procedure ........................................................................................................... ......................35 8.4 extended records............................................................................................................ .......................38 8.5 diagnostics................................................................................................................. .............................42 8.6 setup ....................................................................................................................... ................................42 8.7 lut bypass.................................................................................................................. ...........................42 9 utopia interface.............................................................................................................. ................................43 9.1 incoming utopia cell interface .............................................................................................. ...............44 9.1.1 incoming phy mode (cells received by t8208) .......................................................................44 9.1.2 incoming atm mode (cells received by t8208).......................................................................44 9.2 outgoing utopia cell interface .............................................................................................. ...............45 9.2.1 outgoing phy mode (cells sent by t8208)...............................................................................45 9.2.2 outgoing atm mode (cells sent by t8208) ..............................................................................46 9.3 counters.................................................................................................................... ..............................48 9.3.1 dropped cell counters.................................................................................................... ...........49 9.4 55-byte utopia mode......................................................................................................... ...................49 9.5 shared utopia mode .......................................................................................................... ..................50 9.6 utopia pin modes ............................................................................................................ .....................52 9.6.1 utopia pin modes for 8-bit utopia operation .......................................................................52 9.6.2 utopia pin modes for 16-bit utopia operation .....................................................................56 9.7 utopia clocking ............................................................................................................. .......................58 9.8 option for counters to clear on read........................................................................................ .............58 10 cell bus interface........................................................................................................... ...................................59 10.1 general architecture ....................................................................................................... ........................59 10.2 cell bus frames............................................................................................................ ..........................61 10.3 cell bus routing headers ................................................................................................... ....................64 10.3.1 control cells............................................................................................................ ...................65 10.3.2 data cells............................................................................................................... ....................65 10.3.3 loopback cells........................................................................................................... ................66 10.3.4 multicast routing........................................................................................................ ................66 10.3.5 broadcast routing........................................................................................................ ..............67
agere systems inc. 3 advance data sheet september 2001 atm interconnect celxpres t8208 table of contents (continued) contents page 10.4 cell bus arbitration ....................................................................................................... .......................... 67 10.5 cell bus monitoring........................................................................................................ ......................... 68 10.6 gtl+ logic ................................................................................................................. ............................ 68 10.7 cell bus write and read clocks ............................................................................................. ................ 69 10.8 modify cell bus request priority based on rx phy fifo threshold.................................................... 70 10.9 digital loopback before cell bus ........................................................................................... ................ 70 11 sdram interface.............................................................................................................. ................................ 71 11.1 memory configuration....................................................................................................... ...................... 71 11.2 powerup sequence........................................................................................................... ...................... 71 11.3 sdram interface timing ..................................................................................................... ................... 72 11.4 queuing .................................................................................................................... .............................. 73 11.5 sdram refresh .............................................................................................................. ....................... 80 11.6 sdram throughput........................................................................................................... ..................... 81 12 traffic management........................................................................................................... ............................... 82 12.1 cell loss priority (clp)................................................................................................... ........................ 82 12.2 forward explicit congestion notification (fecn) ............................................................................ ....... 82 12.3 partial packet discard (ppd) ............................................................................................... ................... 83 13 jtag test access port ........................................................................................................ ............................ 84 13.1 instruction register ....................................................................................................... .......................... 84 13.2 boundary-scan register ..................................................................................................... .................... 85 14 registers.................................................................................................................... ....................................... 88 14.1 register types............................................................................................................. ........................... 88 14.2 direct memory access registers ............................................................................................. ............... 92 14.2.1 little-endian format (big_end = 0) for extended memory access registers 30h37h............ 97 14.2.2 big-endian format (big_end = 1) for extended memory access registers 30h37h .............. 99 14.2.3 general-purpose i/o control registers ................................................................................... 1 01 14.2.4 control cells ............................................................................................................ ................ 102 14.2.5 multicast memories ....................................................................................................... ........... 103 14.3 extended memory registers.................................................................................................. ...............103 14.3.1 main registers ........................................................................................................... .............. 103 14.3.2 utopia registers ......................................................................................................... .......... 125 14.3.2.1 tx utopia configuration ......................................................................................... 130 14.3.2.2 tx utopia monitoring .............................................................................................. 175 14.3.2.3 rx utopia count monitoring ................................................................................... 176 14.3.2.4 rx utopia configuration monitoring ....................................................................... 177 14.3.3 sdram registers .......................................................................................................... .......... 179 14.3.3.1 sdram control memory ........................................................................................... 187 14.3.4 various internal memories ................................................................................................ ....... 190 14.3.4.1 control cell memories ............................................................................................... 190 14.3.4.2 multicast number memories ...................................................................................... 191 14.3.4.3 ppd state memory ....................................................................................................193 14.3.5 dropped cell count ....................................................................................................... ..........194 14.3.6 external memories ........................................................................................................ ........... 197 14.3.6.1 look-up translation memory .................................................................................... 197 14.3.6.2 sdram buffer memory .............................................................................................197 15 absolute maximum ratings ..................................................................................................... ....................... 198 16 recommended operating conditions............................................................................................. ................ 198 17 handling precautions......................................................................................................... ............................. 198 18 electrical requirements and characteristics .................................................................................. ................ 199 18.1 crystal information........................................................................................................ ........................ 199 18.2 dc electrical characteristics .............................................................................................. .................... 200
4 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 table of contents (continued) contents page 19 timing requirements .......................................................................................................... ........................... 201 19.1 microprocessor interface timing ............................................................................................ .............. 202 19.2 utopia timing .............................................................................................................. ...................... 208 19.3 external lut memory timing................................................................................................. .............. 209 19.4 cell bus timing ............................................................................................................ ........................ 211 19.5 sdram interface timing..................................................................................................... ................. 212 20 outline diagram .............................................................................................................. ............................... 213 21 ordering information ......................................................................................................... ............................. 214 list of figures figure page figure 1. functional block diagram .............................................................................................. ......................... 10 figure 2. dual bus implementation ............................................................................................... ......................... 11 figure 3. 272-pin pbgatop view ................................................................................................. ..................... 21 figure 4. translation ram memory map8-byte records ............................................................................. ...... 31 figure 5. translation record types8-byte records............................................................................... ............ 32 figure 6. translation ram flow diagram .......................................................................................... .................... 37 figure 7. translation record typesextended mode ................................................................................ .......... 39 figure 8. translation ram memory mapextended mode.............................................................................. ..... 40 figure 9. queue priority multiplexing ........................................................................................... .......................... 48 figure 10. tx utopia cell handling .............................................................................................. ....................... 49 figure 11. tx utopia bus sharing for 8-bit utopia mode .......................................................................... ....... 51 figure 12. tx utopia bus sharing for 16-bit utopia mode ......................................................................... .......52 figure 13. cell bus frame format (bit positions for 16-user mode) ............................................................... ...... 61 figure 14. cell bus frame format (bit positions for 32-user mode) ............................................................... ...... 62 figure 15. cell bus routing headers ............................................................................................. ........................ 64 figure 16. gtl+ external circuitry .............................................................................................. ........................... 68 figure 17. sdram timing parameters .............................................................................................. .................... 72 figure 18. crystal .............................................................................................................. ................................... 199 figure 19. negative resistance plot ............................................................................................. ....................... 199 figure 20. nonmultiplexed intel mode write access timing ................................................................................ 202 figure 21. nonmultiplexed intel mode read access timing................................................................................ 202 figure 22. motorola mode write access timing................................................................................................... 20 4 figure 23. motorola mode read access timing .................................................................................................. 204 figure 24. multiplexed intel mode write access timing....................................................................................... 206 figure 25. multiplexed intel mode read access timing ...................................................................................... 206 figure 26. external lut memory read timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 209 figure 27. external lut memory write timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 209 figure 28. cell bus timing ...................................................................................................... ............................. 211 figure 29. sdram interface timing............................................................................................... ...................... 212
agere systems inc. 5 advance data sheet september 2001 atm interconnect celxpres t8208 list of tables table page table 1. utopia pins ......................................................................................................... ..................................... 14 table 2. shared utopia pins .................................................................................................. ................................ 15 table 3. cell bus pins ....................................................................................................... ....................................... 16 table 4. sdram interface pins ................................................................................................ ................................ 17 table 5. microprocessor interface pins ........................................................................................ ............................ 18 table 6. translation sram interface ........................................................................................... .............................. 19 table 7. jtag pins ........................................................................................................... ........................................ 19 table 8. general-purpose pins ................................................................................................ ................................ 20 table 9. power pins .......................................................................................................... ........................................ 20 table 10. loop filter register settings ....................................................................................... .............................. 24 table 11. access times ....................................................................................................... .................................... 27 table 12. active and ignore truth table ...................................................................................... ............................ 33 table 13. vpi value truth table .............................................................................................. ................................ 34 table 14. oam routing control truth table .................................................................................... ........................ 34 table 15. f5 translation record addresses table8-byte records ................................................................ ....... 35 table 16. f5 translation record addresses tableextended mode ................................................................. ..... 41 table 17. pin configuration for 8-bit utopia ................................................................................. ......................... 53 table 18. pin configuration for 16-bit utopia ................................................................................. ....................... 57 table 19. supported memory configurations .................................................................................... ....................... 71 table 20. queue organization and port group address/priority bits for 32 ports in 8-bit utopia mode ............ 74 table 21. queue organization and port group address/priority bits for 64 ports in 8-bit utopia mode and 32 ports in 16-bit utopia mode .............................................................................................................. 77 table 22. instruction register ............................................................................................... .................................... 84 table 23. boundary-scan register descriptions ................................................................................. ..................... 85 table 24. register map ......................................................................................................... ..................................... 88 table 25. identification 0 (idnt0) (00h) ..................................................................................... .............................. 92 table 26. identification 1 (idnt1) (01h) ...................................................................................... .............................. 92 table 27. identification 2 (idnt2) (02h) ..................................................................................... .............................. 92 table 28. direct configuration/control register (dccr) (28h)................................................................... .............. 93 table 29. interrupt service request (isreq) (29h) ............................................................................ ..................... 94 table 30. mclk pll configuration 0 (mpllcf0) (2ah) ............................................................................ ................ 94 table 31. mclk pll configuration 1 (mpllcf1) (2bh) ........................................................................... ................. 95 table 32. gtl+ slew rate configuration (gtlsrcf) (2eh) ........................................................................ ............ 95 table 33. gtl+ control (gtlcntrl) (2fh) .................................................................................................. ......... 96 table 34. extended memory address 1 (little endian) (ema1_le) (30h) ........................................................... ..... 97 table 35. extended memory address 2 (little endian) (ema2_le) (31h) ........................................................... ..... 97 table 36. extended memory address 3 (little endian) (ema3_le) (32h) ........................................................... ..... 97 table 37. extended memory address 4 (little endian) (ema4_le) (33h) ........................................................... ..... 97 table 38. extended memory access (little endian) (ema_le) (34h) ............................................................... ........ 97 table 39. extended memory data low (little endian) (emdl_le) (36h) ............................................................ ..... 98 table 40. extended memory data high (little endian) (emdh_le) (37h) ........................................................... ..... 98 table 41. extended memory address 4 (big endian) (ema4_be) (30h) .............................................................. .... 99 table 42. extended memory address 3 (big endian) (ema3_be) (31h) .............................................................. .... 99 table 43. extended memory address 2 (big endian) (ema2_be) (32h) .............................................................. .... 99 table 44. extended memory address 1 (big endian) (ema1_be) (33h) .............................................................. .... 99 table 45. extended memory access (big endian) (ema_be) (34h) .................................................................. ..... 100 table 46. extended memory data high (big endian) (emdh_be) (36h) .............................................................. .. 100 table 47. extended memory data low (big endian) (emdl_be) (37h) ............................................................... .. 100 table 48. gpio output enable (gpio_oe) (39h) .................................................................................. ................. 101 table 49. gpio output value (gpio_ov) (3bh) .................................................................................... ................ 101 table 50. gpio input value (gpio_iv) (3dh) .................................................................................... ..................... 101
6 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 list of tables (continued) table page table 51. control cell receive direct memory (ccrxdm) (5ch to 93h) ............................................................ ....102 table 52. control cell transmit direct memory (cctxdm) (a0h to d7h) ........................................................... ....102 table 53. phy port 0 and control cells multicast direct memory (pp0mdm) (e0h to ffh) ...................................103 table 54. main configuration 1 (mcf1) (0100h) ................................................................................. .....................104 table 55. main interrupt status 1 (mis1) (0102h) ............................................................................. ......................105 table 56. main interrupt enable 1 (mie1) (0104h) ............................................................................. .....................106 table 57. tx utopia clock configuration (txuccf) (010ch) ...................................................................... ........107 table 58. rx utopia clock configuration (rxuccf) (010eh) ...................................................................... .......108 table 59. main configuration/control (mcfct) (0110h) .......................................................................... ...............109 table 60. main configuration 2 (mcf2) (0112h) ................................................................................. .....................110 table 61. utopia configuration (ucf) (0114h) ................................................................................. ...................113 table 62. main configuration 3 (mcf3) (0116h) ................................................................................ .....................113 table 63. utopia configuration 5 (ucf5) (0118h) .............................................................................. .................114 table 64. utopia configuration 4 (ucf4) (011ah) .............................................................................. .................114 table 65. utopia configuration 3 (ucf3) (011ch) .............................................................................. .................114 table 66. utopia configuration 2 (ucf2) (011eh) .............................................................................. .................114 table 67. extended lut control (elutcn) (0120h) .............................................................................. ................115 table 68. generated cell bus clocks control register (gcbccr) (0122h) ......................................................... ..116 table 69. rx phy fifo thresholds to change cell bus request priority (rxpftcrp) (0126h) ........................118 table 70. enable request on upper backplane address (erub) (012ch) ........................................................... .119 table 71. enable request on lower backplane address (erlb) (012ch) ............................................................ 119 table 72. cell bus configuration/status (cbcfs) (0130h) ...................................................................... ..............120 table 73. main interrupt status 2 (mis2) (0132h) .............................................................................. ......................121 table 74. main interrupt enable 2 (mie2) (0134h) .............................................................................. .....................122 table 75. loopback (lb) (0136h) .............................................................................................. .............................122 table 76. extended lut configuration (elutcf) (0138h) ........................................................................ ............122 table 77. misrouted cell lut 3 (mlut3) (013ch) ................................................................................ ................. 123 table 78. misrouted cell lut 2 (mlut2) (013eh) ................................................................................ .................. 123 table 79. misrouted cell lut 1 (mlut1) (0140h) ............................................................................... ...................123 table 80. misrouted cell lut 0 (mlut0) (0142h) ............................................................................... ...................123 table 81. misrouted cell lut 4 (mlut4) (0144h) ............................................................................... ...................124 table 82. misrouted cell header high (mchh) (0146h) ........................................................................... .............. 124 table 83. misrouted cell header low (mchl) (0148h) ............................................................................ .............. 124 table 84. hec interrupt status 3 (his3) (0300h) ............................................................................... .................... 125 table 85. hec interrupt status 2 (his2) (0302h) ................................................................................ .................... 125 table 86. hec interrupt status 1 (his1) (0304h) .............................................................................. .....................125 table 87. hec interrupt status 0 (his0) (0306h) .............................................................................. .....................125 table 88. hec interrupt enable 3 (hie3) (0308h) .............................................................................. ....................126 table 89. hec interrupt enable 2 (hie2) (030ah) .............................................................................. ....................126 table 90. hec interrupt enable 1 (hie1) (030ch) .............................................................................. ....................126 table 91. hec interrupt enable 0 (hie0) (030eh) .............................................................................. ....................126 table 92. lut interrupt service request 3 (lutisr3) (0310h) .................................................................. ...........127 table 93. lut interrupt service request 2 (lutisr2) (0312h) .................................................................. ...........127 table 94. lut interrupt service request 1 (lutisr1) (0314ch) ................................................................. ..........127 table 95. lut interrupt service request 0 (lutisr0) (0316h) .................................................................. ...........127 table 96. lut x configuration/status (lutxcfs) (0320h to 039eh) .............................................................. ......128 table 97. master queue 7 (mq7) (0150h) ......................................................................................... ...................... 130 table 98. master queue 6 (mq6) (0152h) ......................................................................................... ...................... 130 table 99. master queue 5 (mq5) (0154h) ......................................................................................... ...................... 130 table 100. master queue 4 (mq4) (0156h) ....................................................................................... ......................131 table 101. master queue 3 (mq3) (0158h) ....................................................................................... ......................131 table 102. master queue 2 (mq2) (015ah) ....................................................................................... ......................131
agere systems inc. 7 advance data sheet september 2001 atm interconnect celxpres t8208 list of tables (continued) table page table 103. master queue 1 (mq1) (015ch) ....................................................................................... ..................... 132 table 104. master queue 0 (mq0) (015eh) ....................................................................................... ..................... 132 table 105. slave queue 7 (sq7) (0160h) ....................................................................................... ....................... 133 table 106. slave queue 6 (sq6) (0162h) ....................................................................................... ....................... 133 table 107. slave queue 5 (sq5) (0164h) ....................................................................................... ....................... 134 table 108. slave queue 4 (sq4) (0166h) ....................................................................................... ....................... 134 table 109. slave queue 3 (sq3) (0168h) ....................................................................................... ....................... 134 table 110. slave queue 2 (sq2) (016ah) ....................................................................................... ....................... 135 table 111. slave queue 1 (sq1) (016ch) ....................................................................................... ...................... 135 table 112. slave queue 0 (sq0) (016eh) ....................................................................................... ....................... 135 table 113. tx phy fifo routing 7 (txpfr7) (0170h) ............................................................................ ............. 136 table 114. tx phy fifo routing 6 (txpfr6) (0172h) ............................................................................ ............. 137 table 115. tx phy fifo routing 5 (txpfr5) (0174h) ............................................................................ ............. 138 table 116. tx phy fifo routing 4 (txpfr4) (0176h) ............................................................................ ............. 139 table 117. tx phy fifo routing 3 (txpfr3) (0178h) ............................................................................ ............. 140 table 118. tx phy fifo routing 2 (txpfr2) (017ah) ............................................................................ ............ 141 table 119. tx phy fifo routing 1 (txpfr1) (017ch) ............................................................................ ............ 142 table 120. tx phy fifo routing 0 (txpfr0) (017eh) ............................................................................ ............ 143 table 121. global bypass sdram control register (gbscr) (01b0h) .............................................................. .. 144 table 122. bypass sdram service request register (bssr) (01beh ) ............................................................. 145 table 123. bypass sdram queue interrupt status register 0 (bsqisr0) (01c0 h) .......................................... 147 table 124. bypass sdram queue interrupt status register 1 (bsqisr1) (01c2 h) .......................................... 148 table 125. bypass sdram queue interrupt status register 2 (bsqisr2) (01c4 h) .......................................... 149 table 126. bypass sdram queue interrupt status register 3 (bsqis30) (01c6h ) .......................................... 150 table 127. bypass sdram queue interrupt status register 4 (bsqisr4) (01c8 h) .......................................... 151 table 128. bypass sdram queue interrupt status register 5 (bsqisr5) (01ca h) .......................................... 152 table 129. bypass sdram queue interrupt status register 6 (bsqisr6) (01cc h) ......................................... 153 table 130. bypass sdram queue interrupt status register 7 (bsqisr7) (01ce h) .......................................... 154 table 131. bypass sdram queue interrupt status register 8 (bsqisr8) (01d0 h) .......................................... 155 table 132. bypass sdram queue interrupt status register 9 (bsqisr9) (01d2 h) .......................................... 156 table 133. bypass sdram queue interrupt status register 10 (bsqisr10) (01d4 h) ...................................... 157 table 134. bypass sdram queue interrupt status register 11 (bsqisr11) (01d6 h) ...................................... 158 table 135. bypass sdram queue interrupt status register 12 (bsqisr12) (01d8 h) ...................................... 159 table 136. bypass sdram queue interrupt status register 13 (bsqisr13) (01da h) ..................................... 160 table 137. bypass sdram queue interrupt status register 14 (bsqisr14) (01dc h) ..................................... 161 table 138. bypass sdram queue interrupt status register 15 (bsqisr15) (01de h) ..................................... 162 table 139. routing information 1 (ri1) (0200h) ............................................................................... ...................... 163 table 140. routing information 2 (ri2) (0202h) ............................................................................... ...................... 164 table 141. routing information 3 (ri3) (0204h) ............................................................................... ...................... 165 table 142. ppd information 1 (ppdi1) (0206h) ................................................................................. .................... 166 table 143. ppd information 2 (ppdi2) (0208h) ................................................................................. .................... 167 table 144. ppd information 3 (ppdi3) (020ah) .................................................................................. .................... 168 table 145. ppd information 4 (ppdi4) (020ch) ................................................................................. .................... 169 table 146. ppd information 5 (ppdi5) (020eh) ................................................................................. .................... 170 table 147. ppd information 6 (ppdi6) (0210h) ................................................................................. .................... 171 table 148. ppd information 7 (ppdi7) (0212h) ................................................................................. .................... 172 table 149. routing information 4 (ri4) (0214h) ............................................................................... ...................... 173 table 150. ppd memory write (ppdmw) (0418h) .................................................................................. .............. 174 table 151. phy port x transmit count structure (ppxtxcnt) (0600h to 06feh) ................................................ 175 table 152. phy port x receive count structure (ppxrxcnt) (4000h to 40feh) ............................................... 176 table 153. phy port x configuration structure (ppxcf) (4200h to 42feh ) ....................................................... 177 table 154. sdram control (sct) (0400h) ....................................................................................... ..................... 179 table 155. sdram interrupt status (sis) (0402h) .............................................................................. ................... 179
8 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 list of tables (continued) tables pages table 156. sdram interrupt enable (sie) (0404h) .............................................................................. ..................179 table 157. sdram configuration (scf) (0408h) ................................................................................. ..................180 table 158. refresh (rfrsh) (0410h) ........................................................................................... ..........................181 table 159. refresh lateness (rfrshl) (0412h) ................................................................................. ..................181 table 160. idle state 1 (is1) (0420h) ........................................................................................ ..............................181 table 161. idle state 2 (is2) (0422h) ........................................................................................ ..............................181 table 162. manual access state 1 (mas1) (0424h) .............................................................................. .................182 table 163. manual access state 2 (mas2) (0426h) .............................................................................. .................182 table 164. sdram interrupt service request 7 (sisr7) (0430h) ................................................................. ........183 table 165. sdram interrupt service request 6 (sisr6) (0432h) ................................................................. ........183 table 166. sdram interrupt service request 5 (sisr5) (0434h) ................................................................. ........183 table 167. sdram interrupt service request 4 (sisr4) (0436h) .................................................................. ....... 183 table 168. sdram interrupt service request 3 (sisr3) (0438h) ................................................................. ........184 table 169. sdram interrupt service request 2 (sisr2) (043ah) ................................................................. ........184 table 170. sdram interrupt service request 1 (sisr1) (043ch) ................................................................. ........184 table 171. sdram interrupt service request 0 (sisr0) (043eh) ................................................................. ........184 table 172. queue x (qx) (0440h to 053eh) ..................................................................................... ......................185 table 173. queue x definition structure (qxdef) (2000h to 2ffeh) ............................................................. .......187 table 174. control cell receive extended memory (ccrxem) (07fch to 0832h) ................................................190 table 175. control cell transmit extended memory (cctxem) (0900h to 0936h) ................................................190 table 176. phy port 0 and control cells multicast extended memory (pp0mem) (0c00h to 0c1eh) ...................191 table 177. phy port x multicast memory (ppxmm) (0c20h to 0ffeh) ............................................................... ..192 table 178. ppd memory (ppdm) (1000h to 13feh) ................................................................................ ..............193 table 179. queue x dropped cell count (qxdcc) (3000h to 31feh ) .................................................................194 table 180. translation ram memory (tram) (100000h to 17fffeh) ................................................................. ...197 table 181. sdram (sdram) (2000000h to 3fffffeh) .............................................................................. .........197 table 182. maximum rating parameters and values ............................................................................... ...............198 table 183. recommended operating conditions ................................................................................... .................198 table 184. hbm esd threshold .................................................................................................. ............................198 table 185. crystal specifications ............................................................................................ ................................199 table 186. external clock requirements ........................................................................................ .........................199 table 187. dc electrical characteristics ..................................................................................... .............................200 table 188. input clocks ...................................................................................................... ....................................201 table 189. output clocks ..................................................................................................... ...................................201 table 190. nonmultiplexed intel mode write access timing ..................................................................................203 table 191. nonmultiplexed intel mode read access timing ..................................................................................203 table 192. motorola mode write access timing .................................................................................................... .205 table 193. motorola mode read access timing ..................................................................................................... 205 table 194. multiplexed intel mode write access timing .........................................................................................207 table 195. multiplexed intel mode read access timing .........................................................................................207 table 196. tx utopia timing (70 pf load on outputs) .......................................................................... .............208 table 197. rx utopia timing (70 pf load on outputs) .......................................................................... .............208 table 198. external lut memory read timing (cyc_per_acc = 2) ................................................................. .......210 table 199. external lut memory read timing (cyc_per_acc = 3) ................................................................. .......210 table 200. external lut memory write timing (cyc_per_acc = 2) ................................................................ ........210 table 201. external lut memory write timing (cyc_per_acc = 3) ................................................................ ........210 table 202. cell bus timing ................................................................................................... ..................................211 table 203. sdram interface timing ............................................................................................ ...........................212
agere systems inc. 9 advance data sheet september 2001 atm interconnect celxpres t8208 1 product overview (continued) 1.3 description the celxpres t8208 device integrates all of the required functionality to transport atm cells across a backplane architecture with high-speed cell traffic exceeding 1.5 gbits/s to a maximum of 32 destinations. the management of multiple service categories and monitoring of performance on atm and phy interfaces is incorporated in the devices functionality. traffic delivery to multi-phys (mphys) is managed through the utopia interface. the t8208 device meets the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications for cell-level handshake and mphy data path operation with rates up to 635 mbits/s. the t8208 supports the required mphy operation as described in sections 4.1 and 4.2 of the atm forums level 2 specification. the t8208 supports mphy operation with one transmit cell available (txclav) signal and one receive cell available (rxclav) signal for up to 16 phy ports for an 8-bit utopia 2 inter- face configuration. with four transmit cells available/enable (txclav/enb*) pairs of signals and receive cell avail- able/enable (rxclav/enb*) pairs of signals, 64 mphys can be supported. for a 16-bit utopia 2 interface configuration, the t8208 supports mphy operation with one transmit cell available (txclav) signal and one receive cell available (rxclav) signal for up to 8 phy ports. with four transmit cell available (txclav/enb*) sig- nals and four receive cell available (rxclav/enb*) signals, 32 mphys can be supported in 16-bit utopia 2 inter- face configuration. in addition to the required utopia signals, the optional transmit parity (txprty) and receive parity (rxprty) signals are provided. the t8208 may be configured as an atm or phy level device providing cell routing between utopia and a 32-bit wide cell bus. in addition to the 32 data signals, the bus has the following signals: n read clock n write clock n frame sync n acknowledge atm cells arriving from the utopia interface may get vpi and vci translation and routing information from a look- up table in external sram. an external synchronous dynamic random access memory (sdram) is used to extend the buffering for atm cells destined for the utopia interface. this external sdram may be partitioned into four or less independently sized queues per phy for a configuration of 32 mphys and two queues per phy or a program- mable number of queues per phy for a configuration of 64 mphys. the four queues may be used to support qual- ity of service (qos) by directing different traffic categories to each queue. the number of cells per queue per phy is programmable. the celxpres t8208 provides a shared utopia mode, which allows two devices on different cell buses to share the same utopia bus in atm mode. using a glueless interface, the two t8208 devices resolve queue priorities and arbitrate the use of the utopia bus. this shared mode can be used to provide redundancy or increase uto- pia traffic capacity by supporting traffic from multiple cell busses. the celxpres t8208 supports the transport of control and loopback cells with an external microprocessor. control or loopback cells may be sent or received through the microprocessor interface. the 8-bit microprocessor interface may be configured to be motorola or intel compatible and is used to configure and monitor the device.
10 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 1 product overview (continued) 5-7542d f figure 1. functional block diagram one or two 32k to 256k x 8 look-up engine rx utopia interface rx phy fifo (16 cells) control cell tx fifo (1 cell) loopback fifo (1 cell) control cell rx fifo (16 cells) tx phy fifo (256 cells) sdram interface tx utopia 1m to 16m x 16 sdram microprocessor interface microprocessor cell bus cell bus arbiter cell bus monitoring cell bus interface cell bus tx utopia interface rx utopia tx utopia (4 cells) input fifo (256 cells) cell buffer (lut) srams rx utopia fifo digital loopback (4 cells) cell bus output fifo (4 cells)
agere systems inc. 11 advance data sheet september 2001 atm interconnect celxpres t8208 1 product overview (continued) figure 2 illustrates the use of the celxpres t8208 in a system with dual backplane cell buses using shared uto- pia mode. in this configuration, both t8208 devices on each card receive cells from the utopia bus, and each device uses its translation table to determine if the cell should be transmitted on its backplane cell bus. in the egress direction, each t8208 device receives cells from its cell bus to transmit on the utopia bus. mphy arbitra- tion and queue priorities are resolved using a six-wire interface between the two devices. although a single atm virtual connection is not typically established on both backplane cell buses simultaneously, no restrictions exist for a single phy utilizing both backplane cell buses for different virtual connections supporting higher throughput from two bus interfaces. redundant bus configurations can be supported in the event of a bus failure with t8208 devices by configuring one device to assume bus responsibility from the other. 0041b figure 2. dual bus implementation downstream buffering upstream translation utopia t8208 downstream buffering upstream translation utopia phys t8208 backplane bus downstream buffering upstream translation utopia t8208 downstream buffering upstream translation utopia phys t8208
12 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 1 product overview (continued) 1.4 conventions n all numbers in this document are decimals unless otherwise specified. n hexadecimal numbers can be identified by the h suffix, e.g., a5h. n binary numbers are either in double quotes for multiple bits or in single quotes for individual bits, e.g., 1001 and 0. n a byte is 8 bits, a word is 16 bits, and a double word (dword) is 32 bits. n a binary value of 1 is high, and a binary value of 0 is low. n to clear is to change one or multiple bit values to 0. n to set is to change one or multiple bit values to 1. n all memory addresses are specified in hexadecimal. n addresses are converted from bytes to words or double words using the little-endian format, unless otherwise specified. n a signal name with a trailing asterisk is active-low, e.g., sd_we*. n bits y to x will be designated bits (y:x).
agere systems inc . 13 advance data sheet september 2001 atm interconnect celxpres t8208 1 product overview (continued) 1.5 glossary bus cell : major content of the cell bus frame consisting of 56 bytes, 4 bytes for routing options and 52 bytes for the atm cell content, which excludes the hec. the bus cell is preceded by the 4 bytes of request and followed by the 4 bytes of grant and parity information. clp : cell loss priority. the clp is a 1-bit field in the cell header that becomes set when the cell violates the negotiated quality of service parameters. efci : explicit forward congestion indication. the efci is a 1-bit field in the pti field of the cell header that becomes set when the cell encounters congestion. fecn : forward explicit congestion notification. fecn is a method used by the network to signal to the destination when congestion is encountered. the efci bit is used to indicate the congestion. gfc : generic flow control. the gfc is a 4-bit field in the cell header that may be used by a uni to support traffic and congestion control. typically, this field is pro- grammed to 0000 indicating that generic flow control is not sup ported. gfc may be used in priority proto- cols. grant section : last 4 bytes of the cell bus frame. the grant section occurs during the last clock cycle of the cell bus frame. during this cycle, the cell bus arbiter indicates which t8208 may transmit during the next bus cell unit of the cell bus frame. a parity vector is also transmitted dur- ing the grant section. hec : header error control. the hec is a 1-byte field in the cell header used for bit error detection and correction in the header. nni : network node interface. the nni is the interface between nodes in the public network. oam cell : operations and maintenance cell. an oam cell carries local management information. ppd : partial packet discard. ppd is a technique to relieve congestion. when one cell in a packet is lost, all remaining cells in the packet, except the last, are dis- carded. pti : payload type identifier. the pti is a 3-bit field in the cell header containing information about the type of data (user, oam, or traffic management) and about encoun- tered congestion. qos : quality of service. quality of service parameters define the performance requirements and characteristics for traffic on an assigned channel. some parameters include cell loss ratio, cell transfer delay, cell delay vari- ation, peak cell rate, and sustained cell rate. request section : first 4 bytes of the cell bus frame. the request section occurs during the first clock cycle of the cell bus frame. during this cycle, 16 t8208 devices assert their trans- mission requests onto the cell bus. rm : resource management. rm is the local management of network resources. rxclav : receive cell available signal as described in the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications. rxenb : receive enable signal as described in the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications. txclav : transmit cell available signal as described in the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications. txenb : transmit enable signal as described in the atm forums universal test and operations phy interface for atm (utopia) level 1, version 2.01 and level 2, version 1.0 specifications. uni : user network interface. the uni is the interface between a private network node and a public network node. vci : virtual channel identifier. the vci is a 2-byte field in the cell header that identifies the virtual channel used by the cell. vpi : virtual path identifier. the vpi is an 8-bit field in the uni cell header or a 12-bit field in the nni cell header that identifies the virtual path of the cell.
14 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout this section defines the celxpres t8208 pins. all ttl compatible inputs or i/o are 5 v tolerant. no gtl+ inputs or i/o are 5 v tolerant. table 1. utopia pins symbol ball reset value type name/description u_rxaddr[4:0] r2, p3, r1, p2, p1 z i/o rx utopia address lines. 10 ma drive, ttl compatible i/o, 5 v tolerant. u_rxdata[15:0] v4, w4, y2, w3, y1, w2, v3, w1, v2, u3, t4, v1, u2, t3, u1, t2 i rx utopia data lines. ttl compatible input, 5 v tolerant. u_rxclk t1 z i/o rx utopia clock. 10 ma drive, ttl compatible i/o, 5 v tolerant. u_rxsoc p4 i rx utopia start of cell (active-high). ttl compatible input, 5 v tolerant. u_rxclav[0] l4 z i/o rx utopia phy 0 cell available (active-high). main rx cell available in single phy mode. 10 ma drive, ttl compatible i/o, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. u_rxclav[3:1] m3, m2, m1 i rx utopia cell available lines (active-high). ttl compatible input, 5 v tolerant. these pins have an internal 50 k w pull-up resis- tor. u_rxenb*[0] m4 z i/o rx utopia phy 0 enable (active-low). main rx enable in sin- gle phy mode. 10 ma drive, ttl compatible i/o, 5 v tolerant. u_rxenb*[3:1] n3, n2, n1 z i/o rx utopia phy enable lines (active-low). 10 ma drive, ttl compatible i/o, 5 v tolerant. u_rxprty r3 i rx utopia odd parity. ttl compatible input, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. u_txaddr[4:0] p17, r19, r20, p18, p19 z i/o tx utopia address lines. 10 ma drive, ttl compatible i/o. 5 v tolerant. u_txdata[15:0] y18, u16, v17, w18, y19, v18, w19, y20, w20, v19, u19, u18, t17, v20, u20, t18 zo tx utopia data lines. 10 ma drive, ttl compatible output. u_txclk r18 z i/o tx utopia clock. 10 ma drive, ttl compatible i/o, 5 v tolerant. u_txsoc t20 z o tx utopia start of cell (active-high). 10 ma drive, ttl compat- ible output. u_txclav[0] m20 z i/o tx utopia phy 0 cell available (active-high). main tx cell available in single phy mode. 10 ma drive, ttl compatible i/o. 5 v tolerant. this pin has an internal 50 k w pull-up resistor. u_txclav[3:1] m17, m18, m19 i tx utopia cell available lines (active-high). ttl compatible input, 5 v tolerant. these pins have an internal 50 k w pull-up resis- tor. u_txenb*[0] n20 z i/o tx utopia phy 0 enable (active-low). main tx enable in single phy mode. 10 ma drive, ttl compatible i/o, 5 v tolerant. u_txenb*[3:1] p20, n18, n19 z o tx utopia enable lines (active-low). 10 ma drive, ttl com- patible output. u_txprty t19 z o tx utopia odd parity. 10 ma drive, ttl compatible output.
agere systems inc. 15 advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 2. shared utopia pins symbol ball reset value type name/description u_shr_grant[1:0] w17, v16 1 i/o shared utopia grant. used for grant if device is shared. utopia master to indicate approval of the requested cell transfer. 6 ma drive, ttl compatible i/o. these pins have an internal 50 k w pull-up resistor. u_shr_req[3:0] b2, b3, c4, d5 1 i/o shared utopia request. used to indicate a cell to be transferred from a requested queue if device is shared utopia slave. 6 ma drive, ttl compatible i/o. these pins have an internal 50 k w pull-up resistor.
16 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 3. cell bus pins symbol ball reset value type name/description ua*[4:0] b18, b17, c17, d16, a18 i unit address lines (active-low). address assigned to device for cell bus identification. ttl compatible input, 5 v tolerant. cb_d*[31:0] b5, c6, d7, a5, b6, c7, a6, b7, a7, c8, b8, a8, d9, c9, b9, a9, a11, c11, b11, a12, b12, c12, d12, a13, b13, c13, a14, b14, c14, a15, b15, d14 z i/o cell bus data lines (active-low). gtl+ i/o. cb_wc* a10 i cell bus write clock (active-low). uses falling edge to output data on cell bus. write and read clocks have the same frequency but different phase. gtl+ input. cb_rc* b10 i cell bus read clock (active-low). uses falling edge to latch data from cell bus. write and read clocks have the same frequency but different phase. gtl+ input. cb_fs* c15 z i/o cell bus frame sync (active-low). gtl+ i/o. cb_ack* b16 z i/o cell bus acknowledge signal (active-low). driven low on cycle 0 of the following frame when a valid cell is received from the cell bus. this signal is not driven for broadcast or multicast cells. gtl+ i/o. arb_en* a17 i cell bus arbiter enable (active-low). cell bus arbiter enable. only one device on the cell bus may be config- ured as arbiter. ttl-compatible input, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. cb_disable* c16 i cell bus disable (active-low). cmos input that 3- states all gtl+ outputs when low, but gtl+ buffer inputs are active. this pin has an internal 50 k w pull-up resistor. cb_iref a4 i cell bus current reference. precision current refer- ence for gtl+ buffers. a 1 k w , 1% resistor must be con- nected between this pin and gnd. cb_vref d10 i cell bus voltage reference. gtl+ buffer threshold voltage reference (1.0 v typical). this voltage reference is 2/3 v tt , created using a voltage divider of three 1 k w , 1% resistors between v tt and cb_vref_vss. cb_vref_vss c10 cell bus voltage reference ground. cb_gen_wc a3 o cell bus generated write clock. ttl compatible (+5 v) driver. 10 ma drive. this is the write clock gener- ated by the t8208 device. read/write clock delay set by register 0122h bits[15:13]. cb_gen_rc b4 o cell bus generated read clock. ttl compatible (+5 v) driver. 10 ma drive. this is the read clock gener- ated by the t8208 device. read/write clock delay set by register 0122h bits[15:13].
agere systems inc. 17 advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 4. sdram interface pins symbol ball reset value type name/description sd_a[11:0] l19, l18, l20, k20, k19, k18, k17, j20, j19, j18, j17, h20 xo sdram address lines. 7 ma drive, ttl compatible out- put. these buffers are 50 w impedance matching buffers. long printed-wiring board traces should have 50 w nominal impedance. sd_d[15:0] f19, e20, g17, f18, e19, d20, e18, d19, c20 e17, d18, c19, b20, c18, b19, a20 z i/o sdram data lines. 7 ma drive, ttl compatible i/o. these buffers are 50 w impedance matching buffers. long printed- wiring board traces should have 50 w nominal impedance. sd_bs[1:0] h18, g20 x o sdram bank selects. 7 ma drive, ttl compatible output. these buffers are 50 w impedance matching buffers. long printed-wiring board traces should have 50 w nominal impedance. sd_ras* g19 1 o sdram row address select (active-low). 7 ma drive, ttl compatible output. this buffer is a 50 w impedance matching buffer. long printed-wiring board traces should have 50 w nominal impedance. sd_cas* f20 1 o sdram column address select (active-low). 7 ma drive, ttl compatible output. this buffer is a 50 w imped- ance matching buffer. long printed-wiring board traces should have 50 w nominal impedance. sd_we* g18 1 o sdram write enable (active-low). 7 ma drive, ttl com- patible output. this buffer is a 50 w impedance matching buffer. long printed-wiring board traces should have 50 w nominal impedance. sd_clk h19 z o sdram clock. 7 ma drive, ttl compatible output. this buffer is a 50 w impedance matching buffer. long printed- wiring board traces should have 50 w nominal impedance. sd_iref a19 i sdram current reference. precision current reference for sdram buffers. a 1 k w , 1% resistor must be connected between this pin and gnd.
18 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 5. microprocessor interface pins symbol ball reset value type name/description a[7:1] w6, y6, v7, w7, y7, v8, w8 i microprocessor port address lines. most significant 7 bits of the address bus. ttl compatible input, 5 v tolerant. a[0]/ale y8 i microprocessor port address 0/address latch enable. least significant bit of the address bus in nonmultiplexed mode or address latch enable in multiplexed mode. d[7:0] u9, v9 w9, y9, w10, v10, y10, y11 z i/o microprocessor port data lines. 6 ma drive, ttl compat- ible i/o, 5 v tolerant. sel* w12 i microprocessor chip select (active-low). ttl compati- ble input, 5 v tolerant. wr*_ds* v12 i microprocessor write/data strobe. active-low write enable in intel mode. active-low data strobe in motorola mode. ttl compatible input, 5 v tolerant. rd*_rw* u12 i microprocessor read/write. active-low read enable in intel mode, or read/write* enable in motorola mode, where read is active-high and write is active-low. ttl compatible input, 5 v tolerant. int_irq* y12 0/1 o cpu interrupt. active-high in intel mode and active-low in motorola mode. 4 ma drive, ttl compatible output. rdy_dtack* u11 z o ready/data transfer acknowledge. active-high ready sig- nal in intel mode and active-low data transfer acknowledge in motorola mode. indicates access complete. 6 ma drive, ttl compatible output. mot_sel y13 i intel / motorola selection. 0 = intel , 1 = motorola . ttl compatible input, 5 v tolerant. mux w13 i microprocessor multiplex select. active-high for multiplex mode. ttl compatible input, 5 v tolerant.
agere systems inc. 19 advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 6. translation sram interface table 7. jtag pins symbol ball reset value type name/description tr_a[17:0] l3, l2, l1, k1, k3, k2, j1, j2, j3, j4, h1, h2, h3, g1, g2, g3, f1, f2 xo translation ram address lines. 4 ma drive, ttl compat- ible output. tr_d[7:0] e3, d1, c1, e4, d3, d2, c2, b1 z i/o translation ram data lines. 4 ma drive, ttl compatible i/o, 5 v tolerant. tr_cs*[1:0] e1, e2 1 o translation ram chip selects (active-low). chip selects to select one of two external srams. for connection to one external device, tr_cs*[0] is used. 4 ma drive, ttl compati- ble output. tr_oe* f3 1 o external ram output enable (active-low). 4 ma drive, ttl compatible output. tr_we* g4 1 o external ram write enable (active-low). 4 ma drive, ttl compatible output. symbol ball reset value type name/description jtag_tdi y16 i test data input (jtag). ttl compatible input, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. jtag_tdo w16 x o test data output (jtag). 4 ma drive, ttl compatible out- put. jtag_trst* w15 i test reset (jtag) (active-low). should be pulled low when part is in normal operation. ttl compatible input, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. jtag_tclk v15 i test clock (jtag). ttl compatible input, 5 v tolerant. this pin has an internal 50 k w pull-up resistor. jtag_tms u14 i test mode select (jtag). ttl compatible input, 5 v toler- ant. this pin has an internal 50 k w pull-up resistor.
20 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) table 8. general-purpose pins table 9. power pins symbol ball reset value type name/description gpio[7:0] u5, y3, y4, v5, w5, y5, v6, u7 i/o general-purpose i/o. 4 ma drive, ttl compatible i/o, 5 v tolerant. these pins have an internal 50 k w pull-up resistor. reset* v14 i reset (active-low). schmitt trigger, ttl compatible input, 5 v tolerant. xtalin v13 i crystal input (pclk). this input may be driven by either a crystal or an external clock. if a crystal is used, connect it between this pin and xtalout and connect the appropriately valued capacitor from this pin to v ss . if an external clock is used, this is a 5 v tolerant cmos input with 50 mhz max input frequency. xtalout y14 o crystal output feedback. if a crystal is used, connect it between this pin and xtalin and connect the appropriately valued capacitor from this pin to v ss . if an external clock is used to drive xtalin, this pin must be left unconnected. cko w11 o buffered clock output. if enabled, pclk is output on this pin. 8 ma drive, ttl compatible output. this pin is high impedance if not enabled. cko_e v11 i cko enable. enable for buffered clock output. if cko is not used, tie this enable pin low. active-high, ttl compatible input, 5 v tolerant. nc a2, a16, c3, c5, y15, y17 no connection. reserved. symbol ball name/description v dd d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 power. 3.3 v. these pins should be properly decoupled using 0.01 m f or 0.1 m f capacitors. v ss a1, d4, d8, d13, d17, h4, h17, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, n4, n17, u4, u8, u13, u17 ground. v dda w14 clock oscillator power. 3.3 v. this pin should be properly decoupled using 0.01 m f or 0.1 m f capacitors.
agere systems inc. 21 advance data sheet september 2001 atm interconnect celxpres t8208 2 pinout (continued) 5-8013(f) m figure 3. 272-pin pbga top view v dd v ss v ss v dd v ss v ss v dd v ss v dd v ss v dd v ss v dd v dd v ss v dd v ss v ss v dd v ss v dd v ss v dd v ss v dd a b c d e f g h j k l m n p r t u v w y 1234567891011121314151617181920 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss
22 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 3 powerup/reset sequence one of the following two methods may be used to reset the t8208: 1. assert the reset* pin low for at least 5 pclk periods or 100 ns, whichever is longer, and then return it high for a hardware reset. for a powerup reset, the reset* pin should be held low for at least 5 pclk periods or 100 ns, whichever is longer, after the power supply ramps to its operating voltage and the crystal oscillator is stable. 2. write both the srst* and srst_reg* bits in the direct configuration/control register (address 28h) to 0, and leave them at that value for at least 1 s to perform a software reset. the device is now in the reset state, and the following start-up procedure must be executed to ensure proper oper- ation: 1. after pclk (xtalin) is provided to the t8208, and the device is in the reset state: a. write the mclk pll configuration 0 and 1 registers at addresses 2ah and 2bh. b. continue after the pll has stabilized in 100 m s. 2. set the srst_reg* bit (to take the main registers out of reset), and program the cyc_per_acc and big_end bits in the direct configuration/control register (address 28h). 3. wait 1 m s for the circuit to stabilize. extended memory accesses may now be performed only to the main register group. 4. write the desired values to the main configuration 1 register (address 0100h), the tx utopia clock configura- tion register (address 010ch), and the rx utopia clock configuration register (address 010eh) in the extended memory registers. these bits should not be modified at a later time without returning to the reset state. 5. program the main configuration 2 register (address 0112h) and the utopia configuration register (address 0114h). these registers should not be modified at a later time without returning to the reset state. 6. program the cb_arb_sel and cb_usr_mode bits in the cell bus configuration/status register (address 0130h). 7. wait one clock period of the slowest clock (cell bus, utopia, or pclk) for the circuit to stabilize. 8. set the srst* bit in the direct configuration/control register (address 28h). 9. wait three clock periods of the slowest clock (cell bus, utopia, or pclk) for the circuit to stabilize. the t8208 device is now out of reset state. 10. initialize the sdram per the sdram specifications. 11. enable the sdram by setting the sdram_en bit in the sdram control register (address 0400h). 12. initialize the lut to benign values (recommended). 13. initialize the multicast memory to all '0' (recommended). 14. program the four routing information registers (addresses 0200h through 0204h and 0214h) and the seven ppd information registers (addresses 0206h through 0212h).
agere systems inc. 23 advance data sheet september 2001 atm interconnect celxpres t8208 4 hot insertion when a connector with proper pin sequencing is used, the agere systems inc. gtl+ buffers withstand hot inser- tion into a backplane without corrupting the cell bus or damaging the device. the ground pins on the connector should extend beyond all other pins so that the ground connections are made first. in addition, the power pins on the connector should extend beyond the signal pins so that the power connections are made before the signal but after the ground connections. during hot insertion, the cell bus is not corrupted because the gtl+ outputs go to a high-impedance state during the powerup reset. therefore, proper timing should be met in the external powerup reset circuit.
24 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 5 pll configuration the frequency of the devices main clock (mclk) is derived from the clock at the xtalin input (pclk) and is given by the following equation when the pll is engaged: f mclk = f pclk x note: when the pll is engaged, mclk is the output of the pll. m and n are the pll_m[4:0] and pll_n[2:0] counter values in the mclk pll configuration 1 register (address 2bh) and must be set so that the voltage-controlled oscillator (vco) operates in the appropriate range. the maximum value for f mclk is 100 mhz. the valid range for m is between 2 and 22 inclusive, and the valid range for n is between 0 and 7 inclusive. when multiple sets of values can achieve the desired result, choose the lowest value of m and the corresponding value for n. note: the output of the pll must always be at least 50 mhz. the loop filter must be set properly for correct operation of the pll. the proper setting of the loop filter bits, lf[3:0], in the mclk pll configuration 0 register (address 2ah) is determined by the chosen value for m. the following table lists the lf[3:0] settings for given values of m. typical pll lock-in time is 50 m s. table 10. loop filter register settings pll configuration example : given a pclk frequency of 50 mhz and a desired mclk frequency of 100 mhz, the proper values of m, n, and lf[3:0] are the following: m = 2 n = 7 lf[3:0] = 0010 the bypass pll (bypb) and pll enable (pllen) bits are used to select the source of mclk for the t8208. to select the output of the pll as the clock, both bits must be programmed to 1, and to select pclk as the clock, both bits must be programmed to 0. m mclk pll configuration 0 (2ah) lf[3:0] 22 0111 1621 0110 1015 0101 69 0100 45 0011 23 0010 m2 + () 2mod8n1 + () 1 + () () ------------------------------------------------------------------
agere systems inc. 25 advance data sheet september 2001 atm interconnect celxpres t8208 6 microprocessor interface 6.1 microprocessor interface configuration the microprocessor interface may be configured for either intel or motorola mode via the mot_sel input. tie mot_sel high to select motorola mode and low to select intel mode. in addition, the address and data buses may be configured for multiplexed or nonmultiplexed mode using the mux input. to select multiplexed mode, tie mux high, and to select nonmultiplexed mode, tie mux low. in multiplexed mode, d[7:0] are used for both the address and the data bus, and the a[0] input becomes an address latch enable (ale) signal. in nonmultiplexed mode, sepa- rate address, a[7:0], and data, d[7:0], buses are used. in both modes, the active-low sel* input selects the device for microprocessor read or write accesses. the data leads are 3-stated when the sel*, wr*_ds*, or rd*_wr* signal is high. in motorola mode, rd*_rw* is a read/write enable signal, which indicates the current access is a read when it is high and a write when low. the wr*_ds* signal is data strobe in motorola mode. the rdy_dtack* output is an active-low data transfer acknowledge signal. the t8208 takes this signal low when the microprocessor access is complete. the rdy_dtack* output returns high when the microprocessor acknowledges the access by taking the sel* or wr*_ds* signal high. the rdy_dtack* output then goes high-impedance. in intel mode, the rd*_rw* input is an active-low read enable signal, and wr*_ds* is an active-low write enable sig- nal. a logic low level on rd*_rw* indicates to the t8208 that the current access is a read, and a logic low level on wr*_ds* indicates the access is a write. finally, the rdy_dtack* output is an active-high ready signal. the t8208 asserts this signal high when a microprocessor access is complete. the rdy_dtack* output then goes high-imped- ance when the sel*, wr*_ds*, or rd*_wr* signal goes high. 6.2 microprocessor interrupts the int_irq* output is an active-high interrupt in intel mode and an active-low interrupt request in motorola mode. in intel mode, int_irq* is normally low and goes high when an interrupt is generated. in motorola mode, the interrupt request signal is normally high and goes low during an interrupt. interrupts are generated when an enabled inter- rupt status bit becomes set. all interrupt status bits in the t8208 have a corresponding interrupt enable bit. when the enable bit is cleared, the corresponding interrupt status bit is not enabled and will not generate an interrupt. several registers containing interrupt status bits exist in the four separate extended memory register groups (main, utopia, sdram, and bypass sdram) of the t8208. the interrupt service request register at direct address 29h indicates which register group is generating the interrupt. only enabled interrupts will cause the int_serv_mainreg, int_serv_sdramreg, and int_serv_utopiareg bits to become set. for the main register group, a special case exists. the ctrl_cell_sent and the ctrl_cell_av interrupts (in the main interrupt status 1 register) do not cause the main group indication bit to be set in the interrupt service request register. these interrupts have their own dedicated service request bits to optimize sending and receiving control cells. the ctrl_cell_sent and ctrl_cell_av bits may become set whether the corresponding interrupt is enabled or not. 6.3 accessing the celxpres t8208 via microprocessor interface the celxpres t8208 has two distinct memory spaces: the direct memory access registers and the extended mem- ory registers. the direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and ffh. the extended memory registers are indirectly addressed and mapped between addresses 0100h and 3fffffeh. the extended memory contains the sdram memory, the translation ram, internal memories, and the devices configuration, status, and control registers. extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. direct memory access registers are located in section 14.2, direct memory access registers, and extended memory registers are located in section 14.3, extended memory registers.
26 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 6 microprocessor interface (continued) 6.3.1 accessing the extended memory registers before accessing the extended memory registers, the powerup sequence, as described in section 3, powerup/ reset sequence, must be completed. accesses to extended memory are word accesses internally; therefore, the least significant bit of the address is always 0. only the most significant 25 bits are supplied to the extended mem- ory address registers (addresses 30h 34h). the following procedure outlines the steps needed for extended memory accesses in the t8208 device. 6.3.1.1 extended memory writes 1. write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. write ext_d [15:8] byte to the extended memory data high register (little endian or big endian) (optional). 6. write ext_d [7:0] byte to the extended memory data low register (little endian or big endian) (optional). 7. write ext_a [5:1] bits; write 01, 10, or 11 to ext_we[1:0]; and write 1 to ext_strt_acc in the extended mem- ory access register (little endian or big endian) (mandatory). 8. read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory). 6.3.1.2 extended memory reads 1. write ext_a [25] bit to the extended memory address 4 register (little endian or big endian) (optional). 2. write ext_a [24:17] byte to the extended memory address register 3 (little endian or big endian) (optional). 3. write ext_a [16:9] byte to the extended memory address register 2 (little endian or big endian) (optional). 4. write ext_a [8:6] bits to the extended memory address register 1 (little endian or big endian) (optional). 5. write ext_a [5:1] bits; write 00 to ext_we[1:0]; and write 1 to ext_strt_acc in the extended memory access register (little endian or big endian) (mandatory). 6. read the extended memory access register (little endian or big endian) to determine that the ext_strt_acc bit has been cleared by hardware (mandatory). 7. read ext_d [15:8] byte from the extended memory data high register (little endian or big endian) (optional). 8. read ext_d [7:0] byte from the extended memory data low register (little endian or big endian) (optional). note: once the ext_strt_acc bit is set by software, only the extended memory access register should be accessed until the ext_strt_acc bit is cleared by hardware.
agere systems inc. 27 advance data sheet september 2001 atm interconnect celxpres t8208 6 microprocessor interface (continued) 6.3.2 celxpres t8208 access performance the times represented in the following table reflect access times for various microprocessor interface reads and writes. for direct access registers, the values represent the time until the rdy_dtack signal transitions indicating the data transfer portion of the access is complete. for accesses to extended memory, the values represent the time from the completion of a write to register 34h until the ext_strt_acc bit is cleared. the actual times are dependent on the frequency of the pclk and mclk clocks (see section 5, pll configuration). the terms pclkp and mclkp in the table represent the period of pclk and mclk, respectively, in ns. table 11. access times description min typ max unit read/write to 28h3dh 4 x pclkp 5 x pclkp 5 x pclkp + 30 ns reads to: 60h93h, a0hd7h, e0hffh (direct internal memory) 6 x pclkp + 3 x mclkp 8 x pclkp + 9 x mclkp 12 x pclkp + 15 x mclkp ns writes to: 60h93h, a0hd7h, e0hffh (direct internal memory) 6 x pclkp 8 x pclkp + 4 x mclkp 10 x pclkp + 9 x mclkp ns reads to extended memory internal structures 6 x pclkp + 6 x mclkp 8 x pclkp + 12 x mclkp 12 x pclkp + 18 x mclkp ns writes to extended memory internal structures 6 x pclkp 8 x pclkp + 7 x mclkp 10 x pclkp + 12 x mclkp ns read from lut sram 4 x pclkp + 11 x mclkp 10 x pclkp + 50 x mclkp ns write to lut sram 4 x pclkp 10 x pclkp + 50 x mclkp ns
28 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 7 general-purpose i/o (gpio) the t8208 has eight programmable general-purpose i/o pins called gpio. these gpio pins may be indepen- dently programmed, via the gpio_oe[7:0] bits in the gpio output enable register (address 39h), to be inputs or outputs. if a gpio_oe bit is set to 1, the corresponding gpio pin is an output, or if cleared to 0, the correspond- ing gpio pin is an input. input values are read from the gpio_in[7:0] bits in the gpio input value register (address 3dh), and output values are written to the gpio_out[7:0] bits in the gpio output value register (address 3bh). the gpio[7:0] pins all have internal 50 k w pull-up resistors.
agere systems inc. 29 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table cells arriving from the utopia bus obtain information from the external static ram look-up table (lut), which is divided among vpi, vci, and oam/rm records. each of these records contains specific vpi or vpi/vci translation and cell bus routing information. the size of the records is programmable to 8 bytes or an extended 16 bytes. the 16-byte mode adds two 32-bit counters to each record. the 16-byte mode is discussed in section 8.4, extended records. the vpi value in the header, in addition to the phy port number, of the incoming cell points to a vpi record in the look-up table. this vpi record is examined first. if the vpi record indicates oam f4 routing, the oam record, to which the vpi record points, provides the oam routing and vpi/vci translation information. if oam f4 routing is not indicated, information about the type of translation, vpi only or vpi/vci, is obtained from the original vpi record. for vpi only translation, routing information is obtained from the vpi record, and full or partial vpi transla- tion is performed. for vpi/vci translation, the vpi record points to the appropriate vci record, where vpi/vci translation and routing information is stored. if the vci record indicates oam f5 routing, the oam record, to which the vci record points, provides the oam routing and vpi/vci translation information. if no oam f5 routing is indicated, vpi/vci transla- tion and cell routing are performed using the information in the vci record. 8.1 look-up table ram the number of memory devices (up to two) used for the look-up table and the size of the external sram are pro- grammable. the tram_qnty_sel bit in the main configuration 1 register (address 0100h) specifies whether one or two ram chips are used. if two memory devices are used, separate chip select signals are generated. these chip selects are created from the decoded ram addresses. the tram_size configuration bits, also in the main configu- ration 1 register, are used to select memory sizes of 32 kbytes, 64 kbytes, 128 kbytes, or 256 kbytes. therefore, the maximum look-up table size of 512 kbytes is realized when two ram chips of 256 kbytes each are used. if a single sram of 512 kbytes is used (instead of two srams of 256 kbytes each), then bit 5 in the main configu- ration 1 register must be set to 1. if a single sram of 512 kbytes is not used, this bit must be cleared to 0.
30 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) 8.2 organization organization is discussed in terms of 8-byte records. differences in organization for 8-byte records and 16-byte records will be discussed in section 8.4, extended records. the look-up table may be configured to support up to 64 ports when multi-phy mode is used, effectively creating a separate look-up table for each port. all vpi, vci, and oam/rm records may be either 8 bytes or 16 bytes in length. (see section 8.4, extended records for information on 16-byte records.) figure 4 shows the translation ram memory map for 8-byte records. oam/rm translation records are located at the bottom of the memory space with 64 oam/rm records used by each port. if the device is configured to support 64 ports, the first 4096 records will be used for oam and rm trans- lation records. this translates to 32 kbytes of memory for 8-byte records. the remaining memory is then used for vpi and vci records. for 8-byte records, the base addresses of the oam records are calculated from the following equation: oba = pn 8 64 in this equation, oba is the oam base address, pn is the port number, 8 is the number of bytes per record, and 64 is the number of records per port. for example, the oam/rm translation records for port 2 will have a base address of 1024 or 400h. note: if the device is configured to use less than 64 ports, the oam/rm translation record memory space will be allocated enough memory to handle ports 0 through the maximum port number used. for example, if the device is configured to use ports 0, 2, 4, and 6 (see section 9, utopia interface), the oam/rm translation record memory space will use 448 records (for ports 0 through 6). oam/rm translation record memory space for ports 1, 3, and 5 will be skipped even though the ports are not used. note: if the device is configured in phy mode (see section 9, utopia interface), the device supports only a single phy and the translation ram memory will be addressed as port 0. separate vpi record base addresses may be set up for each port in multi-phy mode, and the number of incoming vpi bits used as a pointer into the look-up table may be programmed. (see section 14.3, extended memory regis- ters, table 153, phy port x configuration structure (ppxcf) (4200h to 42feh).) for 8-byte records, the total memory used by the vpi records is calculated using the following equation: ms = np x 2 nb x 8 in this equation, ms is the memory size used for vpi records, np is the number of ports used, 8 is the number of bytes per record, and nb is the number of incoming vpi bits used to address the look-up table. this calculated memory space must be reserved for vpi records.
agere systems inc. 31 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) figure 4. translation ram memory map8-byte records the four translation record types (vci, oam/rm, vpi only, and vpi for vpi/vci) for 8-byte records are illustrated in figure 5. there are two types of vpi translation records: one for vpi translation only and one for vpi/vci transla- tion. the vpi only translation record differs from other records in that it has the sh and sl bits which are used to indicate full or partial vpi translation. (see table 13, the vpi value truth table.) the other vpi record is used when vpi/vci translation occurs. it has the vci offset bits and max vci value bits which are used to point to the vci record where translation and routing information reside. the maximum vci offset is 19 bits in length; therefore, only bits 3 through 18 are stored in the vpi record. to address the appropriate vci translation record, the vci from the cells header is multiplied by 8 and added to bits 3 through 18 of the vci offset which is obtained from the vpi record. this sum is the final offset into the look- up table. this final offset should then be added to the translation ram memory beginning address 100000h (table 180) to obtain the final address. the max vci value indicates the maximum number of vci translation records in the table. therefore, if the vci from the cells header is greater than the max vci value, the cells vci is out of range and is counted as a misrouted cell. note that vpi records from different ports may reference the same vci translation record. other control bits in these records are described following figure 5. routing look-up memory map oam cell routing port x record map 0000h oam cell routing port 0 +0000h vp oam vci = 0 (f4) 0200h oam cell routing port 1 0400h oam cell routing port 2 0600h oam cell routing port 3 0800h oam cell routing port 4 +00f8h vp oam vci = 31 (f4) 0a00h oam cell routing port 5 +0100h vp oam vci = 6 & pt = 110 (f4) (rm-vpc) 0c00h oam cell routing port 6 +0108h vc oam pti = 100 (f5) 0e00h oam cell routing port 7 +0110h vc oam pti = 101 (f5) 1000h oam cell routing port 8 +0118h vc oam pti = 110 (f5) 1200h oam cell routing port 9 +0120h vc oam pti = 111 (f5) 1400h oam cell routing port 10 +0128h reserved +0130h reserved 7a00h oam cell routing port 61 7c00h oam cell routing port 62 7e00h oam cell routing port 63 +01f8h reserved 8000h any purpose look-up memory shared between each of the 64 ports 7ffffh
32 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) figure 5. translation record types8-byte records vpi only translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a p e i vpi[11:0] +2 sh sl reserved +4 cell bus routing header[15:0] +6 tandem routing header[15:0] vpi for vpi/vci translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a p e i reserved +2 bits 3 through 18 of vci offset[15:0] +4 max vci value[15:0] +6 reserved vci translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a e i vpi[11:0] +2 vci[15:0] +4 cell bus routing header[15:0] +6 tandem routing header[15:0] oam/rm translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a c1 c0 i vpi[11:0] +2 vci[15:0] +4 cell bus routing header[15:0] +6 tandem routing header[15:0]
agere systems inc. 33 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) the routing control bits for vpi, vci, and oam/rm records are described below: n active (a). this bit is one when the vpi or vci is considered active. see the truth table (table 12) below. this bit is used in all types of records. n ignore (i). when this bit is one, the vpi or vci is ignored. see the truth table (table 12) below. this bit is used in all types of records. if masking the i bit is required (when the i bit is set to 1), then the mask_ignore bit (bit 13 in register 0112h) can be used to achieve this masking. when this bit is set to 1, the t8208 ignores the ignore bit that was programmed in the look-up records that con- trol the translation of the incoming utopia cells. this can be used for redundancy if desired. for redundancy, the software can populate the look-up tables of two t8208 devices (one active and one inactive for redundancy). the ignore (i) bit needs to be set in both the active and inactive devices. the active device has the mask_ignore bit = 1 and the inactive device has the mask_ignore bit = 0. this way the inactive device will not count, route or translate the incoming cells (ignores them). when the active device fails, its mask_ignore bit becomes 0 and the inactive device becomes active by setting its mask_ignore bit = 1. the failed device now will no longer try to count, route, or translate incoming cells, and the new active device takes over cell routing and vpi/vci transla- tion. table 12. active and ignore truth table ai action 0 0 the cell is discarded, considered misrouted, and counted as a received cell. 0 1 the cell is discarded, is not flagged as misrouted, and is not counted as a received cell. 1 0 the cell is valid and is counted as a received cell. 1 1 the cell is discarded, is not flagged as misrouted, and is not counted as a received cell.
34 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) n enable oam/rm routing (e). when this bit is 1 in the vpi record and the vci is less than 32, the routing and translation information is obtained from the appropriate oam/rm f4 record. if this bit is 1 in the vci record and the most significant bit of the pti in the cell header is 1, the routing and translation information is obtained from the appropriate oam/rm f5 record. this bit is used only in vpi and vci records. n vpi translation (p). when this bit is 1, translation is on the vpi only. when this bit is 0, vpi/vci translation is performed. this bit is used only in vpi records. n vpi value high (sh). when this bit is 1, bits 8 through 11 of the incoming vpi are replaced with the correspond- ing bits in the vpi record. see the truth table (table 13) below. this bit is used in vpi only translation records. n vpi value low (sl). when this bit is 1, bits 0 through 7 of the incoming vpi are replaced with the corresponding bits in the vpi record. see the truth table (table 13) below. this bit is used in vpi only translation records. table 13. vpi value truth table n oam routing control (c1, c0). these 2 bits determine if the cell is routed as oam/rm and if vpi/vci translation is performed. see the truth table (table 14) below. these bits are used only in oam/rm records. table 14. oam routing control truth table 1. the most significant 4 bits of the vpi will only be substituted if the global rplc_gfc bit in the direct configuration/contro l register (address 28h) is set in uni mode or if the port is configured in nni mode. sh sl action 0 0 no vpi translation is performed. 01 vpi translation is performed only on bits 07 of the incoming vpi. 1 0 vpi translation is performed only on bits 811 of the incoming vpi. 1 1 complete vpi translation is performed. c1 c0 action 0 0 both incoming vpi and vci are substituted with the vpi 1 and vci, respectively, in the oam/rm record, and the cell is routed according to the cell bus and tandem routing headers in the oam/rm record. 0 1 the cell is not routed as oam/rm. if the record is oam/rm f5, the cell is translated and routed according to the cell bus and tandem routing headers in the original vci record. if the record is oam/ rm f4, the cell is translated and routed according to the cell bus and tandem routing headers in the original vpi record. 1 0 the incoming vpi and vci will be preserved, and the cell is routed according to the cell bus and tan- dem routing headers in the oam/rm record. 11reserved.
agere systems inc. 35 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) 8.3 look-up procedure look-up procedure is discussed in terms of 8-byte records. differences in look-up procedures for 8-byte records and 16-byte records will be discussed in section 8.4, extended records. when a cell is received, the set lutx_vpi_mask bits in the phy port x configuration structure (table 153) indicate which incoming vpi bits are used to address the vpi record in the look-up table. the selected incoming vpi bits are multiplied by eight (for 8-byte records) to create an offset into the table. the sum of this offset and the vpi base address, found in the phy port x configuration structure, creates the actual look-up table address for the vpi record associated with the cell. note that only bits 3 through 18 of the vpi base address are stored in the phy port x configuration structure. if the lutx_vpi_chk bit is set, all unused vpi bits in the cell header must be 0, or the cell will be considered out of range. if the port is configured as uni, the upper four vpi bits (gfc field) will be ignored in the verification. when the cell is out of range, it is discarded and not counted as a received cell. the validity of the accessed vpi record is determined by checking its active (a) and ignore (i) bits. if the cell is valid, the enable oam/rm routing (e) bit is consulted to determine if f4 type oam cell treatment should occur. (see the definition for these bits in section 8.2, organization.) when the e bit is set and the incoming vci is less than 32, the oam record associated with the cell is read. to cal- culate the translation record address for the oam/rm cell, the incoming vci is multiplied by eight (for 8-byte records), and the resulting product is added to the ports oam base address. (see section 8.2, organization.) a special case exists when the incoming vci is six and the pti in the cell header is 110. for this case, the oam translation record address is the sum of the ports oam base address and 100h. next, the validity of the f4 oam record is determined by checking its a and i bits. if it is valid, the cell is routed as described by the oam routing control (c1, c0) bits. (see the definition for these bits in section 8.2, organization.) if the e bit in the vpi record is not one or if the c1 and c0 bits in the oam record are zero and one, respectively, the cell does not receive oam routing. if the cell is not routed oam, the virtual path routing bit (p bit) in the original vpi is checked to determine if the cell receives vpi only or vpi/vci routing. if the p bit indicates vpi only routing, the cell's vpi is replaced as indicated by the switch vpi high and low (sh, sl) bits in the vpi only translation record. (see the definition for these bits in section 8.2, organization.) the cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus. if the p bit indicates vpi/vci routing, the vci translation record is accessed using the vci offset and max vci value bits in the vpi for vpi/vci translation record. (the vci offset and max vci value bits are described in sec- tion 8.2, organization.) again, the validity of the vci translation record is determined by checking its a and i bits. next, if the cell is valid, the e bit in the vci record and the most significant bit of the pti value in the cell header are examined to determine if f5 type oam cell treatment should occur. the value of the incoming cells pti and port number determines the address in the oam/rm record space. the following table outlines the look-up table offsets used for 8-byte records. the oam translation record address is the sum of this offset and the ports oam base address. table 15. f5 translation record addresses table 8-byte records pti oam translation offset 100 ports oam base address plus 108h 101 ports oam base address plus 110h 110 ports oam base address plus 118h 111 ports oam base address plus 120h
36 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) next, the validity of the f5 oam record is determined by checking its a and i bits. if it is valid, the cell is routed as described by the oam routing control (c1, c0) bits. (see the definition for these bits in section 8.2, organization.) if the e bit in the vci record is not one or if the c1 and c0 bits in the oam record are zero and one, respectively, the cell does not receive oam routing. if the cell is not routed as an oam cell, information in the vci translation record is used to route the cell. the cell's vpi and vci are replaced with the vpi and vci, respectively, in the vci record. the most significant 4 bits of the vpi will only be substituted if the global rplc_gfc bit in the direct configura- tion/control register (address 28h) is set or if the port is configured in nni mode. the cell bus routing header and tandem routing header are then added to the cell, and the cell is transmitted on the cell bus. note: unused oam cell routing records in the lut memory space can be used for other purposes.
agere systems inc. 37 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) this look-up procedure is outlined in the flow diagram below. 5-7781f and 5-7782f figure 6. translation ram flow diagram cell in read vpi unused from atm cell header vpi bits all 0 or lutx_vpi_check = 0? a bit = 1 and i bit = 0? e bit = 1 and vci < 32? read vp oam record a bit = 1 and i bit = 0? c1 & c0 = 00 ? c1 & c0 = 10 ? p bit = 1 ? vci cell discarded cell discarded no no yes yes yes yes cell discarded no yes no yes yes no no vpi/vci translation; routing from oam record vpi/vci preserved; routing from oam record no vpi translation; routing from vp record read vpi record vci read vci from atm cell header vci in range? a bit = 1 and i bit = 0? e bit = 1 and pti[2] = 1? yes no read vc oam record a bit = 1 and i bit = 0? yes cell discarded no c1 & c0 = 00 ? c1 & c0 = 10 ? yes no yes no vpi/vci translation; routing from oam record vpi/vci preserved; routing from oam record vpi/vci translation; routing from vc record cell discarded cell discarded no no yes yes read vci record
38 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) 8.4 extended records the length of the translation records may be extended to 16 bytes to support two cell counts for each translation record. the lut_rec_form bits in the extended lut configuration register (address 0138h) are used to select this extended mode. in extended (16-byte) mode, two 32-bit counters are appended to the 8-byte records. the first counter in the translation record, total cell count, keeps a total count of all incoming cells received from the utopia bus whether ultimately routed or discarded except those in which the vpi is out of range. see the defini- tion of the a and i bits in section 8.2, organization. the second counter, special cell count, is a subset of the total cell count counter. this counter counts only cells whose pti and clp values in the cell header match the values specified in the extended lut control register (address 0120h). for example, this counter may be used to track specific f5 type oam/rm cells and cells indicat- ing forward congestion (efci = 1) or lower priority (clp = 1).
agere systems inc. 39 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) the four translation record types for extended mode are illustrated in figure 7 below. figure 7. translation record typesextended mode extended vpi only translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a p e i vpi[11:0] +2 sh sl reserved +4 cell bus routing header[15:0] +6 tandem routing header[15:0] +8 total cell count[31:16] +a total cell count[15:0] +c special cell count[31:16] +e special cell count[15:0] extended vpi for vpi/vci translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a p e i reserved +2 bits 3 through 18 of vci offset[15:0] +4 max vci value[15:0] +6 reserved +8 reserved +a reserved +c reserved +e reserved extended vci translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a e i vpi[11:0] +2 vci[15:0] +4 cell bus routing header[15:0] +6 tandem routing header[15:0] +8 total cell count[31:16] +a total cell count[15:0] +c special cell count[31:16] +e special cell count[15:0] extended oam/rm translation record b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 +0 a c1 c0 i vpi[11:0] +2 vci[15:0] +4 cell bus routing header[15:0] +6 tandem routing header[15:0] +8 total cell count[31:16] +a total cell count[15:0] +c special cell count[31:16] +e special cell count[15:0]
40 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) because the translation records are larger in extended mode, the look-up table memory map changes, the transla- tion record address calculations change, and the memory size calculations change. figure 8 shows the new trans- lation ram memory map for 16-byte records when the device is configured for 64 phy ports. figure 8 . translation ram memory mapextended mode routing look-up memory map oam cell routing port x record map 0000h oam cell routing port 0 +0000h vp oam vci = 0 (f4) 0400h oam cell routing port 1 0800h oam cell routing port 2 0c00h oam cell routing port 3 1000h oam cell routing port 4 +01f0h vp oam vci = 31 (f4) 1400h oam cell routing port 5 +0200h vp oam vci = 6 & pt = 110 (f4) (rm-vpc) 1800h oam cell routing port 6 +0210h vc oam pti = 100 (f5) 1c00h oam cell routing port 7 +0220h vc oam pti = 101 (f5) 2000h oam cell routing port 8 +0230h vc oam pti = 110 (f5) 2400h oam cell routing port 9 +0240h vc oam pti = 111 (f5) 2800h oam cell routing port 10 +0250h reserved +0260h reserved f400h oam cell routing port 61 f800h oam cell routing port 62 fc00h oam cell routing port 63 +03f0h reserved 10000h any purpose look-up memory shared between each of the 64 ports 7ffffh
agere systems inc. 41 advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) the oam/rm translation records at the bottom of the memory map now use 64 kbytes of memory when the device is configured to support 64 mphy ports, and the base addresses for the oam records are now calculated using the following equation: oba = pn 16 64 in this equation, oba is the oam base address, pn is the port number, 16 is the number of bytes per record, and 64 is the number of records per port. to calculate the 16-byte translation record address for the f4 type oam cell, the incoming vci is multiplied by 16, and the resulting product is added to the ports oam base address. for the special case when the incoming vci is six and the pti in the cell header is 110, the oam translation record address is the sum of the ports oam base address and 200h. the 16-byte oam type f5 translation record offset is determined from the incoming cells pti using the following table. the oam translation record address is the sum of this offset and the ports oam base address. table 16. f5 translation record addresses table extended mode in extended mode, the memory space used by the vpi records also changes. the total memory now used by the vpi records is calculated using the following equation: ms = np x 2 nb x 16 in this equation, ms is the memory size used for vpi records, np is the number of ports used, 16 is the number of bytes per record, and nb is the number of incoming vpi bits used to address the look-up table. to address the 16-byte vpi translation record, the selected incoming vpi bits (see section 8.3, look-up proce- dure) are multiplied by 16 to create an offset into the look-up table. the sum of this offset and the vpi base address creates the actual vpi translation record address associated with the incoming cell. note that only bits 3 through 18 of the vpi base address are stored in the phy port x configuration structure. to address the 16-byte vci translation record, the vci from the cells header is multiplied by 16 and added to bits 3 through 18 of the vci offset, which is obtained from the vpi record. this sum is the final offset into the look-up table. this final offset should then be added to the translation ram memory beginning address 100000h (table 180) to obtain the final address. pti oam translation offset 100 ports oam base address plus 210h 101 ports oam base address plus 220h 110 ports oam base address plus 230h 111 ports oam base address plus 240h
42 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 8 look-up table (continued) 8.5 diagnostics the t8208 also includes diagnostics to track misrouted cells. a cell is considered misrouted if its a and i bits are 00, if its vci is out of range, or if the lutx_vpi_chk bit is 1 and the unused vpi bits in the incoming cell header are not all zero (see section 8.3, look-up procedure). when a misrouted cell is detected, the misrouted cell header high and low registers (addresses 0146h and 0148h) may be updated. if enabled, the mis_cell interrupt, the vci_or interrupt, or the vpi_or interrupt will be generated as appropriate (see table 96 in section 14.3, extended memory registers). the misrouted cell header high and low registers contain the first four header bytes of selected misrouted cells. only a misrouted cell from a port whose mis_cell_lut_sel bit is set will update these registers, and this misrouted cell will update the registers only if it is the first received after the mis_cell_clr bit is set. the lst_mis_cell_lut bits indicate the port from which the header bytes in the misrouted cell header high and low registers were received. the mis_cell_lut_sel bits are located in the misrouted lut 0, 1, 2, and 3 registers (addresses 0142h, 0140h, 013eh, and 013ch respectively). the mis_cell_clr, mis_cell_latch, and lst_mis_cell_lut bits are located in the mis- routed lut 4 register (address 0144h). (see tables 77, 78, 79, 80, and 81 in section 14.3, extended memory reg- isters, for a complete description of the above bits.) 8.6 setup when configuring the lut_en bits in the lut x configuration/status register (addresses 0320h through 039eh), care must be taken to ensure that the enabled ports luts correspond to the ports chosen in utopia mode. (see sec- tion 9.6, utopia pin modes.) if a lut is not enabled, corresponding bits in the phy port x configuration structure (section 14.3.2.4, rx utopia configuration monitoring, table 153) will be ignored. also, when the device is con- figured for utopia phy mode (see section 9, utopia interface), only port 0 entries in the external ram look-up table are used; therefore, the look-up table should be set up accordingly. 8.7 lut bypass this feature allows the elimination of the sram (which has the lut information) in implementations that can pro- vide the cell bus routing header (cbrh) and the tandem routing header (trh) to the t8208 device. this feature is enabled when bit 6 in register 0100h is set to 1. when this lut bypass feature is enabled, the t8208 is expecting 58-byte cells in 16-bit utopia mode and 57-byte cells in 8-bit utopia mode on rx utopia. if bit 7 in register 0100h is cleared to 0, then the t8208 device expects to see the trh before the cbrh on the incoming cells. but, if bit 7 in register 0100h is set to 1, the t8208 device expects to see the cbrh before the trh on the incoming cells.
agere systems inc. 43 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface the celxpres t8208 supports the atm forums utopia level 1 and level 2 specifications for cell-level handshake and mphy operation with rates up to 635 mbits/s. the device may be configured as an atm layer or as a phy layer by programming the phyen* bit in the main configuration 1 register (address 0100h). the device may be configured for 16 data bit operation by setting utopia_16 bit (bit 7) in register 0112h. if the uto- pia-16 bit (bit 7) in register 0112h is cleared to 0, then the tx and rx utopia interfaces of the t8208 are config- ured for 8 data bit operation. in utopia 2, 16 bit data mode, a maximum of 32 mphys (64 queues) are supported. in utopia 2, 8-bit data mode, a maximum of 64 mphys (128 queues) are supported. as an atm layer, the device may interface with a single phy layer or multiple phy layers (up to 64). also as an atm layer, it may be configured for shared utopia mode for 64 (8-bit data mode) or 32 (16-bit data mode) mphys. (note that if shared utopia mode is not used, the slave_en bit in the main configuration/control register (address 0110h) must be cleared at device setup.) in phy mode, the t8208 functions as a single phy device on the utopia bus or as one of 31 phy devices on the utopia level 2 bus. in addition to the required utopia signals, the t8208 supports an additional three transmit and three receive enable (u_txenb*[3:1] and u_rxenb*[3:1]) signals, an additional three transmit and three receive cell available (u_txclav[3:1] and u_rxclav[3:1]) signals, a transmit parity (u_txprty) signal, and a receive parity (u_rxprty) signal. the t8208 utopia signal names begin with u_tx, for utopia transmit, or u_rx, for utopia receive. refer- ences to transmit or receive are made relative to the utopia data flow for the atm layer utopia interface. therefore, signals starting with u_rx, such as u_rxenb*[3:0] and u_rxdata[15:0], are receive utopia sig- nals for devices in atm mode but are transmit utopia signals for devices in phy mode. furthermore, sig- nals such as u_txclav[3:0] and u_txaddr[4:0] are transmit utopia signals for devices in atm mode but are receive utopia signals for devices in phy mode. the above atm to phy terminology will be used throughout this utopia interface section.
44 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.1 incoming utopia cell interface 9.1.1 incoming phy mode (cells received by t8208) in phy mode, only one enable (u_rxenb*[0]) signal and one cell available (u_rxclav[0]) signal are used. the u_rxenb*[0] signal is an input connected to the atm layers txenb* signal, and the u_rxclav[0] signal is an output connected to the atm layers txclav signal. as a phy device, the t8208 uses only the lut 0 configuration/status register (address 0320h) and phy port 0 configuration structure register (addresses 4200h4202h). for utopia level 2 functionality, the phy address is programmed in the addr_match bits of the utopia configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be pro- grammed to any value mentioned in the register except 0000. as specified in the utopia level 2 specification, during the polling process, the t8208 drives the u_rxclav[0] signal during the clock cycle following the cycle in which its address appears on the u_rxaddr pins. the u_rxclav[0] pin goes high impedance when not selected to support mphy operation. in utopia level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to 0000, the u_rxaddr pins must be grounded, and the addr_match bits cleared. when the t8208 device is in phy mode, if bit 5 (dont_inhibit_rxphy_clav) of register 0112h is cleared to 0, the rx_clav signal is deasserted if the rx utopia fifo is considered full. if this bit is set to 1, the t8208 keeps the rx_clav signal always asserted high indicating the capability to accept cells even if the rx utopia fifo could overrun, or is actually overrun. 9.1.2 incoming atm mode (cells received by t8208) in atm mode, the t8208 may connect to phy devices that either meet level 1 or level 2 utopia specifications. if the connection is to devices that meet only utopia level 1 specifications, the t8208 may access up to four of these phy devices using the four enable (u_rxenb*[3:0]) and cell available (u_rxclav[3:0]) signals. connection to more than one phy device is possible only if the phys data, start of cell, and parity outputs go high impedance when the device is not enabled. polling of the cell available signals usually occurs while the current cell is received. if the t8208 connects to phy devices meeting level 2 utopia specifications, in 8-bit data mode, up to 64 mphy ports may be accessed. in 8-bit utopia 2 mode, 64 mphys are supported with four rxclav/rxenb pairs with 16-port addressing per rxclav/rxenb pair. for 32 phy ports, two rxclav/rxenb pairs support two groups of 16 phy ports for a total of 32 phy ports. in 16-bit utopia 2 mode, the t8208 supports 32 phys with four rxclav/rxenb pairs with 8-port addressing per rxclav/rxenb pair. in atm mphy mode, the u_rxdata[15:0], u_rxaddr[4:0], u_rxsoc, and u_rxprty signals are connected to each phy port. in addition, the t8208 generates the address (u_rxaddr[4:0]) signals, permitting selection and arbitration among the mphy ports. the number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (all five address lines must be connected to provide for the null address.) refer to section 9.6, utopia pin modes, for more information about the possible combinations of address, cell available, and enable signals. the utopia specification for operation with one txclav and one rxclav is used when the t8208 connects to multiple level 2 phy devices. whether the t8208 is connected to several level 1 or level 2 phy devices, a round robin algorithm is implemented that ensures that all phy devices are serviced (accessed) in a timely manner. in addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer. in atm mode, all unused u_rxclav inputs require connection to ground. note: the u_rxenb outputs are high impedance during powerup and reset. an attached phy may interpret this high-impedance state as an enable; however, the t8208 is not ready to properly handle input data during this time. attach pull-up resistors to these outputs if a problem is anticipated. when the t8208 is in atm mode, if bit 6 (inhibit_rxuto_fifo_overrun) of register 0112h is set to 1, t he t8208 pre- vents the rx utopia fifo from overflowing by deasserting its rx_enb* signal even though the rx_clav signal is high when polled, if the rx utopia fifo is considered full. if this bit is cleared to 0, the rx_enb* signal is not deasserted even if the rx utopia fifo is considered full.
agere systems inc. 45 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.2 outgoing utopia cell interface 9.2.1 outgoing phy mode (cells sent by t8208) in phy mode, only one enable (u_txenb*[0]) signal and one cell available (u_txclav[0]) signal are used. the u_txenb*[0] signal is an input connected to the atm layers rxenb* signal, and the u_txclav[0] signal is an output connected to the atm layers rxclav signal. as a phy device, the t8208 may use queue group 0 (queues 0, 1, 2, and 3) in the sdram and tx utopia cell buffer. the div_queue bits in the main configuration 2 register (address 0112h) may be programmed to 000 for 4 queues or 111 for 1 queue, and the port_rte[127:0] bits in the tx phy fifo routing 0, 1, 2, 3, 4, 5, 6, and 7 registers (addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017ah, 017ch, and 017eh) must be programmed to zero. if only queue 0 is used, configure and use only the queue 0 registers at addresses 0440h and 2000h through 2016h. also, if only queue 0 is used, program the mphy_select bits and priority_select bits in the routing information 1, 2, 3, and 4 registers addresses 0200h, 0202h, 0204h, and 0214h to the zero value of 110000. if queues 0, 1, 2, and 3 are used, configure and use only the queue 0, 1, 2, and 3 reg- isters at addresses 0440h through 0446h and 2000h through 2076h. also, if queues 0, 1, 2, and 3 are used, only the mphy_select bits in the routing information 1, 2, and 4 registers (addresses 0200h, 0202h, and 0214h) must all be programmed to the zero value of 110000. for utopia level 2 functionality, the phy address is programmed in the addr_match bits of utopia configuration register (address 0114h), and the addr_clav_en bits of the main configuration 2 register (address 0112h) can be programmed to any value mentioned in the register except 0000. as specified in the utopia level 2 specifica- tion, the t8208 drives the u_txclav[0] signal during the clock cycle following the one with its address on the u_txaddr pins. the u_txclav[0] pin goes high impedance when not selected to support mphy operation. when the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) is cleared, the u_txsoc, u_txdata[7:0], and u_txprty outputs go high impedance when not selected, allowing multiple phys to be connected on the same uto- pia bus. in utopia level 1, the above level 2 bits are not meaningful; therefore, the addr_clav_en bits must be programmed to 0000, the u_txaddr pins must be grounded, and the addr_match bits cleared. note: if the sdram is bypassed, the tx utopia cell buffer in the t8208 device can be divided into a minimum of 1 queue and a maximum of 128 queues. note: even though the outgoing (egress) queues are 0 3, the egress port is determined by the address match bits in register 0114h.
46 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.2.2 outgoing atm mode (cells sent by t8208) in atm mode, the t8208 may connect to phy devices that either meet level 1 or level 2 utopia specifications. if connection is to devices that meet only utopia level 1 specifications, the t8208 may access up to four of these phy devices using the four enable (u_txenb*[3:0]) and cell available (u_txclav[3:0]) signals. polling of the cell avail- able signals occurs while the current cell is transmitted. if the t8208 connects to phy devices meeting level 2 utopia specifications, in 8-bit data mode, up to 64 mphy ports may be accessed. in 8-bit utopia 2 mode, 64 mphys are supported with four txclav/txenb pairs with 16-port addressing per txclav/txenb pair. for 32 phy ports, two txclav/txenb pairs support two groups of 16 phy ports for a total of 32 phy ports. in 16-bit utopia 2 mode, the t8208 supports 32 phys with four txclav/txenb pairs with 8-port addressing per txclav/txenb pair. in atm mphy mode, the u_txdata[15:0], u_txaddr[4:0], u_txsoc, and u_txprty signals are connected to each phy port. in addition, the t8208 generates the address (u_txaddr[4:0]) signals, permitting selection and arbitration among the mphy ports. the number of address lines used in the connection may vary from one to four, giving a maximum address value of 15. (all five address lines must be connected to provide for the null address.) refer to section 9.6, utopia pin modes, for more information about the possible combinations of address, cell avail- able, and enable signals. the utopia specification for operation with one txclav and one rxclav is used when the t8208 connects to multiple utopia 2 phy devices. in atm mode, all unused u_txclav inputs require connection to ground. note: the u_txenb outputs are high impedance during powerup and reset. an attached phy may interpret this high-impedance state as an enable; however, the t8208 is not ready to send data during this time. attach pull-up resistors to these outputs if a problem is anticipated. the tx utopia cell buffer holds the next cells to be transmitted onto the utopia bus. this tx utopia cell buffer, which holds 256 cells, may be divided into 1, 4, 8, 16, 32, 64, or 128 queues using the div_queue bits in the main configuration 2 register (address 0112h). the number of ports that the t8208 supports determines the number of queues that should be chosen. (see section 9.6, utopia pin modes.) the number of cells per queue, held by the buffer, is determined by dividing 256 (maximum number of cells that tx utopia cell buffer holds) by the number of queues selected (e.g., two cells per queue for 128 queues and 64 cells per queue for four queues).
agere systems inc. 47 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) each port is assigned four queues in the tx utopia cell buffer except in the case of 64 ports (for 8-bit utopia) and 32 ports (for 16-bit utopia). in the case of 64 ports (for 8-bit utopia) and 32 ports (for 16-bit utopia), each port is assigned two queues or a programmable number of queues per phy. each group of four queues is priority encoded where the lowest-numbered queue has the highest priority. groups of four queues are shared among two ports as follows: n queues 03 are shared between ports 0 and 1. n queues 47 are shared between ports 2 and 3. n queues 811 are shared between ports 4 and 5. n queues 1215 are shared between ports 6 and 7. n queues 1619 are shared between ports 8 and 9. n queues 2023 are shared between ports 10 and 11. n queues 2427 are shared between ports 12 and 13. n queues 2831 are shared between ports 14 and 15. n queues 3235 are shared between ports 16 and 17. n queues 3639 are shared between ports 18 and 19. n queues 4043 are shared between ports 20 and 21. n queues 4447 are shared between ports 22 and 23. n queues 4851 are shared between ports 24 and 25. n queues 5255 are shared between ports 26 and 27. n queues 5659 are shared between ports 28 and 29. n queues 6063 are shared between ports 30 and 31. n queues 6467 are shared between ports 32 and 33. n queues 6871 are shared between ports 34 and 35. n queues 7275 are shared between ports 36 and 37. n queues 7679 are shared between ports 38 and 39. n queues 8083 are shared between ports 40 and 41. n queues 8487 are shared between ports 42 and 43. n queues 8891 are shared between ports 44 and 45. n queues 9295 are shared between ports 46 and 47. n queues 9699 are shared between ports 48 and 49. n queues 100103 are shared between ports 50 and 51. n queues 104107 are shared between ports 52 and 53. n queues 108111 are shared between ports 54 and 55. n queues 112115 are shared between ports 56 and 57. n queues 116119 are shared between ports 58 and 59. n queues 120123 are shared between ports 60 and 61. n queues 124127 are shared between ports 62 and 63.
48 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) if 32 or less ports in 8-bit utopia and 16 or less ports in 16-bit utopia are used, then each port uses four queues with priorities from 0 to 3, where 0 is the highest priority. the lowest-numbered queue in the group of four is assigned priority 0, and the highest-numbered queue in the group is assigned priority 3. for 64 phy ports in 8-bit utopia and 32 phy ports in 16-bit utopia, any of the four queues in each group may be assigned to either the even or odd-numbered port. an example, which will be called normal 64-port mode, assigns queues with priorities of 0 and 2 to the even-numbered ports and queues with priorities of 1 and 3 to the odd-numbered ports. the config- uration of queues to ports is supported by port-rte[127:112] to [15:0] bits in the tx phy fifo routing 7 to 0 register structures. please see addresses 0170h through 017eh (tables 113 through 120). figure 9 illustrates the selection of ports when 64 are used. 5-7784.c f figure 9. queue priority multiplexing the tx utopia cell buffer is kept full by cells transferred to it from the sdram. each port has equal priority for transmitting onto the utopia bus. the cell transmitted by any one port is determined by the priority of its queues with cells waiting to be transmitted. in addition, the number of clock cycles wasted for bus arbitration is minimized because polling is performed during cell transfer. cells arriving from the cell bus have their header error check (hec) bytes removed. therefore, the t8208 calcu- lates the hec and inserts it into each cell before transmitting it onto the utopia bus. see figure 10. 9.3 counters for each port selected in mphy mode, two 16-bit registers (in_cnt_phyx[31:16] and in_cnt_phyx[15:0] in table 152) are used as a 32-bit free-running incoming cell counter. each port's counter counts valid and misrouted incoming cells. incoming cells are not counted if they encounter an ignore (i) bit in their translation records that is 1 or if their vpi and/or vci are out of range. the counter for port 0 is found at addresses 4000h and 4002h. see table 152 in section 14.3.2.3, rx utopia count monitoring, for the addresses of other ports' incoming cell counters. also, for each port selected in mphy mode, two 16-bit registers (out_cnt_phyx[31:16] and out_cnt_phyx[15:0] in table 151) are used as a 32-bit free-running outgoing cell counter. each port's counter counts all outgoing cells to the utopia bus. the counter for port 0 is found at addresses 0600h and 0602h. see table 151 in section 14.3.2.2, tx utopia monitoring, for the addresses of other ports' outgoing cell counters. cell bus 256 cell fifo queue 0 queue 1 queue 2 queue 3 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p62 p63 tx utopia port priority port_rte[127:112], port_rte[15:0] in tx phy fifo routing 70 registers starting at address 0170h queue 124 queue 125 queue 126 queue 127 hp lp demultiplexer controlled by
agere systems inc. 49 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.3.1 dropped cell counters there is a 24-bit counter for each queue in the t8208 device that counts all dropped cells. the counter for queue 0 is found at addresses 3000h and 3002h. drop_cell_cnt [15:0] (at address 3002h) and drop_cell_cnt [23:16] (at address 3000h) count the number of dropped cells for queue 0. drop_cell_cnt_ovfl (bit 8 in register 3000h), when set to 1, indicates that the drop cell counter has overflowed since last read by the microprocessor if clear_on_read is enabled. drop_cell_cnt_clp0 (bit 9 in register 3000h), when set to 1, indicates that the clp = 0 cells have been discarded since last read by the microprocessor if clear_on_read is enabled. the drop cell counters for the remaining queues (1 to 127) are at addresses 3004h to 31feh. 9.4 55-byte utopia mode in this special utopia mode, the t8208 transmits a 55-byte cell, as opposed to 53 bytes, on the utopia bus. the extra 2 bytes are the tandem routing header received with the cell from the cell bus. these 2 bytes are appended to the beginning of the cell with the tandem routing header [15:8] byte first, followed by the tandem routing header [7:0] byte. clearing the sp_utopia_sel* bit in the main configuration 1 register (address 0100h) enables this mode. the start of cell signal (u_txsoc) is asserted only once with the first tandem routing header byte. the t8208 may be configured for 55-byte utopia mode whether it is an atm or phy device or in 8-bit or 16-bit utopia mode (bit 7 in register 112h). modified from 5-7783af figure 10. tx utopia cell handling external sdram sdram controller queue fill manager efci insertion fecn ena queue 0 tx utopia cell buffer (2 cells) queue 1 tx utopia cell buffer (2 cells) queue 126 tx utopia cell buffer (2 cells) queue 127 tx utopia cell buffer (2 cells) hec insertion 53-byte cell to tx utopia
50 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.5 shared utopia mode the shared utopia mode allows two t8208 devices on different cell buses to share the same utopia bus. shared utopia mode functionality requires the t8208 devices to be configured for atm mode. this configuration is supported for both utopia level 1 and 2 configurations. the shared mode can be used to provide system back- plane redundancy or to increase the cell bus system capacity. one t8208 device is configured as master and the other as slave, using the slave_en bit in the main configuration/control register (address 110h). the master and the slave communicate to each other through the shared utopia pins; u_shr_grant[1:0] and u_shr_req[3:0]. for the master, u_shr_grant[1:0] functions as the grant outputs for the cell of specific queue to be sent, and the u_shr_req[3:0] pins function as the request inputs to identify which cell of the 128 queues is to be sent. for the slave, u_shr_grant[1:0] functions as the grant input, and u_shr_req[3:0] as the request output. the configuration for the addr_clav_en bits must be the same in both devices in mcf2 (0112h) and port_rte (0170h to 017eh) registers. note : the t8208 will support shared utopia mode for up to 128 queues (64 mphys) in 8-bit utopia mode and will support only 64 queues (32 mphys) in 16-bit utopia mode. the tx utopia cell buffers in the master and the slave may be divided into the same number of queues or differ- ent number of queues. the register settings for mast_queue_in[127:112], mast_queue_in[111:96], mast_queue_in[95:80], mast_queue_in[79:64] mast_queue_in[63:48], mast_queue_in[47:32], mast_queue_in[31:16], mast_queue_in[15:0] and slav_queue_in[127:112], slav_queue_in[111:96], slav_queue_in[95:80], slav_queue_in[79:64] slav_queue_in[63:48], slav_queue_in[47:32], slav_queue_in[31:16], and slav_queue_in[15:0] must be configured in the master device. these bits indicate which queues in the master and which queues in the slave are enabled. the master's priority algorithm uses its mast_queue_in information to determine which waiting cell should be transmitted. the slav_queue_in (0160h to 016eh) registers are ignored in the slave. the transmit operation in shared utopia mode is illustrated in figure 11 for 8-bit utopia mode and figure 12 for 16-bit utopia mode. for the transmit interface, all enable, start of cell, and data signals occur relative to the low- going start of grant signal from the master. the start of grant signal occurs every 60 clock cycles for 8-bit utopia mode and 34 clock cycles for 16-bit utopia mode and is always preceded by at least six clock cycles of ones. both devices can transmit on the tx utopia bus; the master arbitrates the bus and grants the slave access via the u_shr_grant pins. when the slave has cells waiting for transmission, it makes a request for each queue (up to 128 in 8-bit utopia mode and 64 in 16-bit utopia mode) that contains cells. to make this request, the slave pulls its u_shr_req pins low for one clock cycle during the queue's request period. the request clock period for each queue is assigned relative to the master's start of grant signal. the request period for first group of queues occurs ten clock cycles after the falling edge of the start of grant. in 8-bit utopia mode, the next 31 clock cycles evaluate queues 4 to 127 and a low bit for the corresponding queue in the 128 queues represents the queue containing a cell to be sent. in 16-bit utopia mode, the next 15 clock cycles evaluate queues 4 to 63 and a low bit for the cor- responding queue in the 64 queues represents the queue containing a cell to be sent. the master uses the received queue requests and a priority algorithm to determine if a slave's cell should be trans- mitted before one of its own. both master and slave have an equal chance to transmit cells if the cells have equal priority. the first bit in grant[0] is the low-going grant signal. the next six clock cycles designate the queue number of the cell to be transmitted which only requires 7 of the bits to represent any of the 128 queues in 8-bit utopia mode and 6 bits to represent any of the 64 queues in 16-bit utopia mode. the additional bits in the six clock cycles are reserved. the slave then has 53 cycles (8-bit utopia mode) or 27 cycles (16-bit utopia mode) or 55/28 cycles to transmit its cell depending on the mode.
agere systems inc. 51 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) in utopia receive mode, the master controls the utopia bus, and the slave only monitors the bus. both master and slave receive all cells and use their individual look-up tables to determine which cells are destined for their cell bus. the master controls the enable (u_rxenb[3:0]) and address (u_rxaddr[4:0]) signals to the utopia bus. the slave monitors these signals to determine when the cell starts and which port is sending the cell. in shared utopia mode, the master always drives the u_rxaddr[4:0], u_txaddr[4:0], u_txsoc, u_rxenb*[3:0], and u_txenb*[3:0] signals. these signals become high impedance on the slave when the slave_en bit in the main con- figuration/control register (address 0110h) is set. both the master and slave drive the u_txprty and u_txdata[7:0] signals when they transmit a cell; therefore, these signals must go high impedance when not active. clear the tx_utopia_hi_z bit in the main configuration 1 register (address 0100h) to force the u_txprty and u_txdata[7:0] sig- nals to a high-impedance state when inactive. 5-7786bf figure 11. tx utopia bus sharing for 8-bit utopia mode xh0h1h2 p46p47 p44 p46 p47 p45 x qs[6] r[0] qs[4] qs[2] qs[0] invalid invalid qr0 qr4 qr8 u_txclk u_txenb * u_txsoc u_txdata[7:0] u_txprty grant[0] request[0] invalid invalid qr1 qr5 qr9 request[1] invalid invalid qr2 qr6 qr10 request[2] invalid invalid qr3 qr7 qr11 request[3] valid qs[5] qs[3] qs[1] grant[1]
52 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 5-7786cf figure 12. tx utopia bus sharing for 16-bit utopia mode 9.6 utopia pin modes 9.6.1 utopia pin modes for 8-bit utopia operation in multi-phy mode, the t8208 interfaces with up to 64 phy ports in 8-bit utopia operation. each port is num- bered and accessed using a certain combination of the cell available/enable (clav/enb*) and address (addr) sig- nals. the addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. table 17 indicates the port numbering for each of the possible configurations for 8-bit utopia operation. the first selection of zero address and four cell available/enable signals (a value of 0000 in bits 3:0 of register 0112h) is used for connection to utopia level one devices. use this selection to connect from one to four phy devices to the t8208 in atm mode. if only one phy is connected, any of the four cell available signals may be con- nected to the phy. for two phy devices, connect any two, (internal port number must be matched to the clav being used). all unused u_rxclav inputs require connection to ground. four queues are allocated per phy in this configuration. the second selection of one address and four cell available/enable signals (a value of 0010 in bits 3:0 of register 0112h) is used for connection to utopia level two devices. the selection may be used for up to four phy groups of two ports each. (see appendix 1 of the atm forum technical committee utopia level 2, version 1.0 specifi- cation.) all unused u_rxclav inputs require connection to ground. four queues are allocated per phy in this config- uration. x p40/41 x r[0] qs[4] qs[2] qs[0] invalid invalid qr0 qr4 qr8 u_txclk u_txenb * u_txsoc u_txdata[15:0] u_txprty grant[0] request[0] invalid invalid qr1 qr5 qr9 request[1] invalid invalid qr2 qr6 qr10 request[2] invalid invalid qr3 qr7 qr11 request[3] valid qs[5] qs[3] qs[1] grant[1] p42/43 p44/45 p46/47 h0/1 h2/3 hec/00 p46/47 p44/45
agere systems inc. 53 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) the third selection of two address and four cell available/enable signals (a value of 0101 in bits 3:0 of register 0112h) is used for connection to four utopia level 2 phy groups of four ports each. four queues are allocated per phy in this configuration. the fourth selection of four address and two cell available/enable signals (a value of 0011 in bits 3:0 of register 0112h) is used for connection to two utopia level 2 phy groups of sixteen ports each. all unused u_rxclav inputs require connection to ground. four queues are allocated per phy in this configuration. the fifth selection of three address and four cell available/enable signals (a value of 1011 in bits 3:0 of register 0112h) is used for connection to four utopia level 2 phy groups of eight ports each. four queues are allocated per phy in this configuration. the sixth selection of four address and four cell available/enable signals (a value of 1000 in bits 3:0 of register 0112h) is used for connection to four utopia level 2 phy groups of sixteen ports each. two queues are allocated per phy if the normal 64-port mode described in section 11.4 queuing is used or a programmable number of queues can be allocated per phy based on the settings in registers 0170h017eh. table 17. pin configuration for 8-bit utopia # of addr # of clav/enb* ports 07 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 0 4 enb*[0], clav[0], addr = 0 enb*[1], clav[1], addr = 0 enb*[2], clav[2], addr = 0 enb*[3], clav[3], addr = 0 1 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 2 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 2 2 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 6 4 2 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 1 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 3 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 5 enb*[0], clav[0], addr = 6 enb*[0], clav[0], addr = 7 3 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 6 4 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 1 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 3 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 5 enb*[0], clav[0], addr = 6 enb*[0], clav[0], addr = 7 # of addr # of clav/enb* ports 815 port 8 port 9 port 10 port 11 port 12 port 13 port 14 port 15 04 1 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 2 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 2 2 4 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 6 4 2 enb*[0], clav[0], addr = 8 enb*[0], clav[0], addr = 9 enb*[0], clav[0], addr = 10 enb*[0], clav[0], addr = 11 enb*[0], clav[0], addr = 12 enb*[0], clav[0], addr = 13 enb*[0], clav[0], addr = 14 enb*[0], clav[0], addr = 15 3 4 enb*[0], clav[0], addr = 8 enb*[0], clav[0], addr = 10 enb*[0], clav[0], addr = 12 enb*[0], clav[0], addr = 14 4 4 enb*[0], clav[0], addr = 8 enb*[0], clav[0], addr = 9 enb*[0], clav[0], addr = 10 enb*[0], clav[0], addr = 11 enb*[0], clav[0], addr = 12 enb*[0], clav[0], addr = 13 enb*[0], clav[0], addr = 14 enb*[0], clav[0], addr = 15
54 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) table 17. pin configuration for 8-bit utopia (continued) # of addr # of clav/enb* ports 1623 port 16 port 17 port 18 port 19 port 20 port 21 port 22 port 23 04 14 2 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 2 enb*[2], clav[2], addr = 4 enb*[2], clav[2], addr = 6 4 2 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 1 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 3 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 5 enb*[1], clav[1], addr = 6 enb*[1], clav[1], addr = 7 3 4 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 6 4 4 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 1 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 3 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 5 enb*[1], clav[1], addr = 6 enb*[1], clav[1], addr = 7 # of addr # of clav/enb* ports 2431 port 24 port 25 port 26 port 27 port 28 port 29 port 30 port 31 04 14 2 4 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 2 enb*[3], clav[3], addr = 4 enb*[3], clav[3], addr = 6 4 2 enb*[1], clav[1], addr = 8 enb*[1], clav[1], addr = 9 enb*[1], clav[1], addr = 10 enb*[1], clav[1], addr = 11 enb*[1], clav[1], addr = 12 enb*[1], clav[1], addr = 13 enb*[1], clav[1], addr = 14 enb*[1], clav[1], addr = 15 3 4 enb*[1], clav[1], addr = 8 enb*[1], clav[1], addr = 10 enb*[1], clav[1], addr = 12 enb*[1], clav[1], addr = 14 4 4 enb*[1], clav[1], addr = 8 enb*[1], clav[1], addr = 9 enb*[1], clav[1], addr = 10 enb*[1], clav[1], addr = 11 enb*[1], clav[1], addr = 12 enb*[1], clav[1], addr = 13 enb*[1], clav[1], addr = 14 enb*[1], clav[1], addr = 15 # of addr # of clav/enb* ports 3239 port 32 port 33 port 34 port 35 port 36 port 37 port 38 port 39 04 14 24 42 3 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 2 enb*[2], clav[2], addr = 4 enb*[2], clav[2], addr = 6 4 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 1 enb*[2], clav[2], addr = 2 enb*[2], clav[2], addr = 3 enb*[2], clav[2], addr = 4 enb*[2], clav[2], addr = 5 enb*[2], clav[2], addr = 6 enb*[2], clav[2], addr = 7
agere systems inc. 55 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) table 17. pin configuration for 8-bit utopia (continued) # of addr # of clav/enb* ports 4047 port 40 port 41 port 42 port 43 port 44 port 45 port 46 port 47 04 14 24 42 3 4 enb*[2], clav[2], addr = 8 enb*[2], clav[2], addr = 10 enb*[2], clav[2], addr = 12 enb*[2], clav[2], addr = 14 4 4 enb*[2], clav[2], addr = 8 enb*[2], clav[2], addr = 9 enb*[2], clav[2], addr = 10 enb*[2], clav[2], addr = 11 enb*[2], clav[2], addr = 12 enb*[2], clav[2], addr = 13 enb*[2], clav[2], addr = 14 enb*[2], clav[2], addr = 15 # of addr # of clav/enb* ports 4855 port 48 port 49 port 50 port 51 port 52 port 53 port 54 port 55 04 14 24 42 3 4 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 2 enb*[3], clav[3], addr = 4 enb*[3], clav[3], addr = 6 4 4 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 1 enb*[3], clav[3], addr = 2 enb*[3], clav[3], addr = 3 enb*[3], clav[3], addr = 4 enb*[3], clav[3], addr = 5 enb*[3], clav[3], addr = 6 enb*[3], clav[3], addr = 7 # of addr # of clav/enb* ports 5663 port 56 port 57 port 58 port 59 port 60 port 61 port 62 port 63 04 14 24 42 3 4 enb*[3], clav[3], addr = 8 enb*[3], clav[3], addr = 10 enb*[3], clav[3], addr = 12 enb*[3], clav[3], addr = 14 4 4 enb*[3], clav[3], addr = 8 enb*[3], clav[3], addr = 9 enb*[3], clav[3], addr = 10 enb*[3], clav[3], addr = 11 enb*[3], clav[3], addr = 12 enb*[3], clav[3], addr = 13 enb*[3], clav[3], addr = 14 enb*[3], clav[3], addr = 15
56 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.6.2 utopia pin modes for 16-bit utopia operation in multi-phy mode, the t8208 interfaces with up to 32 phy ports in 16-bit utopia operation. each port is num- bered and accessed using a certain combination of the cell available/enable (clav/enb*) and address (addr) sig- nals. the addr_clav_en bits in the main configuration 2 register (address 0112h) are used to select this combination of cell available/enable and address signals. table 18 indicates the port numbering for each of the possible configurations for 16-bit utopia operation. the first selection of zero address and four cell available/enable signals (a value of 0000 in bits 3:0 of register 0112h) is used for connection to utopia level one devices. use this selection to connect from one to four phy devices to the t8208 in atm mode. if only one phy is connected, any of the four cell available signals may be con- nected to the phy. for two phy devices, connect any two. all unused u_rxclav inputs require connection to ground. four queues are allocated per phy in this configuration. the second selection of one address and four cell available/enable signals (a value of 0010 in bits 3:0 of register 0112h) is used for connection to utopia level two devices. the selection may be used for up to four phy groups of two ports each. (see appendix 1 of the atm forum technical committee utopia level 2, version 1.0 specifi- cation.) all unused u_rxclav inputs require connection to ground. four queues are allocated per phy in this config- uration. the third selection of two address and four cell available/enable signals (a value of 0101 in bits 3:0 of register 0112h) is used for connection to four utopia level 2 phy groups of four ports each. four queues are allocated per phy in this configuration. the fourth selection of three address and four cell available/enable signals (a value of 1001 in bits 3:0 of register 0112h) is used for connection to four utopia level 2 phy groups of eight ports each. two queues are allocated per phy if the normal 64-port mode described in section 11.4 queuing is used or a programmable number of queues can be allocated per phy based on the settings in registers 0170h017eh.
agere systems inc. 57 advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) table 18. pin configuration for 16-bit utopia # of addr # of clav/enb* ports 07 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 0 4 enb*[0], clav[0], addr = 0 enb*[1], clav[1], addr = 0 enb*[2], clav[2], addr = 0 enb*[3], clav[3], addr = 0 1 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 2 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 2 2 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 6 3 4 enb*[0], clav[0], addr = 0 enb*[0], clav[0], addr = 1 enb*[0], clav[0], addr = 2 enb*[0], clav[0], addr = 3 enb*[0], clav[0], addr = 4 enb*[0], clav[0], addr = 5 enb*[0], clav[0], addr = 6 enb*[0], clav[0], addr = 7 # of addr # of clav/enb* ports 815 port 8 port 9 port 10 port 11 port 12 port 13 port 14 port 15 04 1 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 2 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 2 2 4 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 6 3 4 enb*[1], clav[1], addr = 0 enb*[1], clav[1], addr = 1 enb*[1], clav[1], addr = 2 enb*[1], clav[1], addr = 3 enb*[1], clav[1], addr = 4 enb*[1], clav[1], addr = 5 enb*[1], clav[1], addr = 6 enb*[1], clav[1], addr = 7 # of addr # of clav/enb* ports 1623 port 16 port 17 port 18 port 19 port 20 port 21 port 22 port 23 04 14 2 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 2 enb*[2], clav[2], addr = 4 enb*[2], clav[2], addr = 6 3 4 enb*[2], clav[2], addr = 0 enb*[2], clav[2], addr = 1 enb*[2], clav[2], addr = 2 enb*[2], clav[2], addr = 3 enb*[2], clav[2], addr = 4 enb*[2], clav[2], addr = 5 enb*[2], clav[2], addr = 6 enb*[2], clav[2], addr = 7 # of addr # of clav/enb* ports 2431 port 24 port 25 port 26 port 27 port 28 port 29 port 30 port 31 04 14 2 4 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 2 enb*[3], clav[3], addr = 4 enb*[3], clav[3], addr = 6 3 4 enb*[3], clav[3], addr = 0 enb*[3], clav[3], addr = 1 enb*[3], clav[3], addr = 2 enb*[3], clav[3], addr = 3 enb*[3], clav[3], addr = 4 enb*[3], clav[3], addr = 5 enb*[3], clav[3], addr = 6 enb*[3], clav[3], addr = 7
58 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 9 utopia interface (continued) 9.7 utopia clocking all tx utopia signals in the t8208 are clocked on the rising edge of the tx utopia clock, and all rx utopia signals are clocked on the rising edge of the rx utopia clock. the utopia specifications state that the atm layer supplies the transmit and receive utopia interface clocks to the phy layers. the t8208 may be configured to drive these clocks or to be driven by them. in the t8208, the clocks for transmit and receive utopia interfaces may be independently derived from several sources. in addition, each of these clocks may be independently configured. the tx utopia clock configuration (address 010ch) and rx utopia clock configuration (address 010eh) registers are used to select and configure the transmit utopia interface and the receive utopia interface clocks, respectively. see these register descrip- tions for more information. 9.8 option for counters to clear on read all the counters (addresses 0600h06feh, 3000h31feh, 4000h40feh, and total and special cell counters of the look-up record if the extended records mode is selected) can be cleared automatically when read by the micro- processor, if the clear_on_read bit (bit 12 in register 0112h) is set to 1. both the registers for every phy (and every queue for dropped cell count) must be read consecutively, (bits 31:16 first, bits 15:0 next) so that both the registers can be cleared automatically. if this bit (bit 12 in register 0112h) is cleared to 0 then the microprocessor will have to clear the counters individu- ally by writing a 0 to them after reading, if it is needed.
agere systems inc. 59 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface 10.1 general architecture the high bandwidth, 32-bit cell bus is used to interconnect t8208 devices. up to 32 devices may be connected to the bus, and cell exchange may occur between any of these devices. each cell bus frame is 16 clock cycles, and during these 16 cycles, one cell is transmitted. the t8208 is designed to operate with a maximum cell bus fre- quency of 66 mhz, which translates to a cell bandwidth of 1.7 gbits/s. the maximum achievable frequency for a given bus implementation is dependent on loading and other design considerations. in addition to the 32 bits of data, the cell bus uses four additional control signals. the four signals include a read clock, a write clock, a frame synchronization signal, and an acknowledge signal. the read and write clocks (cb_rc* and cb_wc* pins, respectively) establish the timing for reading and writing cells on the bus and can be generated internally from the t8208 device or from an external clock source. the internal clock source offers the capability to program the required timing skew between write and read clocks. separate pins are provided for the read and write clock signals. the read clock is used to read the cell from the cell bus, and the write clock is used to write the cell to the cell bus. because all devices on the cell bus read and write on the same clock edge, the write clock is delayed slightly, relative to the read clock, to ensure sufficient data hold time. the active-low frame sync (cb_fs*) is generated by the bus arbiter and indicates the first cycle of the cell bus frame in 16-user mode or the first cycle of two cell bus frames for 32-user mode. this signal is generated every 16 clock cycles for 16-user mode or every 32 clock cycles for 32-user mode. the acknowledge (cb_ack*) signal is used to acknowledge the successful receipt of a cell. this signal is asserted low during the next request cycle by the t8208 that receives the cell. this signal is not asserted for multicast or broadcast cells. in the event of an overflow in the control cell rx fifo, the loopback fifo, the tx phy fifo, or the cell bus input fifo, the acknowledge signal will assert low. in the case of an overflow, this signal will not assert low for multicast and broadcast cells. when cb_disable* is asserted, the device can receive data on the cb_d*[31:0] but cannot transmit data. the device cannot assert the cb_ack* even when a valid cell is received from the cell bus, if cb_disable* is asserted. several t8208 devices may reside on the cell bus, but one device must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. the cell bus arbiter receives requests for access to the bus from all resident devices during the first cycle of the cell bus frame and grants one of these requests during the last cycle of the cell bus frame. before issuing the grant and while a cell is transmitted on the cell bus, the arbiter executes its arbitration algorithm to determine the next device to transmit on the bus. the arbiter also generates the frame synchronization signal. software will designate only one device as cell bus arbiter, at any given time, to ensure proper operation of the bus. a 5-bit unit address is assigned to each device (up to 32) on the bus. each device uses this address to request cell transmission and to identify incoming cells destined for them. each device is given a unique unit address by indi- vidually tying each address (ua*[4:0]) input high or low. the unit address inputs are active-low; therefore, a device with its ua*[4:0] inputs tied to 10000 has address 15. each device can also be given a unique unit address by writing the address into bits 4:0 in register 0130h, provided bit 7 in register 0130h is also set to 1. the device makes a cell transmission request by driving the two assigned bits during the request cycle, which is the first cycle of a frame. for example, device 15 uses bits 30 and 31 of the request cycle as its request bits. (see section 10.2, cell bus frames.) also, each device uses its unit address to determine if a received cell is destined for it. (see section 10.3, cell bus routing headers.)
60 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) the cell bus may be configured for 16-user or 32-user mode, using the cb_usr_mode bit in the cell bus configura- tion/status register (address 0130h). in 16-user mode, all 16 devices assert their transmission requests during the first cycle of each frame, and the transmission grant for the next frame is given during the last cycle of the frame. in 32-user mode, the frame synchronization signal is asserted every two cell bus frames. the two frames are termed the odd and even frames. the frame synchronization signal marks the beginning of the even frame, and the odd frame starts 16 clock cycles later. during the request cycle of the even frame, devices zero through 15 assert their transmission requests, and during the request cycle of the odd frame, devices 16 through 31 assert theirs. requests received from odd and even frames are serviced as a group, and grants are given in the order that the requests are received with the highest priority serviced first with the same priority requests serviced using a round robin algorithm. transmission grants for the next frame are always given at the end of the current frame. cells to be transmitted onto the cell bus come from three sources internal to the t8208. data cells from the uto- pia bus are placed in the rx phy fifo to await transmission onto the cell bus. control cells from the microproces- sor wait in the control cell tx fifo, and loopback cells from the cell bus wait in the loopback fifo. cells from these three fifos are priority multiplexed onto the cell bus output fifo to be transmitted onto the cell bus. optional high priority can be established for data cells or control cells sent to the cell bus. if bit 9 in register 0130h is cleared to 0 then cells from the rx phy fifo have the highest priority, cells from the control cell tx fifo have next highest, and finally, cells from the loopback fifo have the lowest. if bit 9 in register 0130h is set to 1, then cells from the control cell tx fifo have the highest priority, cells from the rx phy fifo have the next highest pri- ority, and finally, cells from the loopback fifo have the lowest priority. this bit on default is 0. incoming cells may be broadcast, multicast, or single address types. the t8208 receiving device accepts single address cells with an address field in the cell bus routing header that matches the devices unit address. in addi- tion, the device accepts all broadcast cells and certain multicast cells that it is configured to accept. (see section 10.3.4, multicast routing.) before a cell is accepted, a check is done on the previous grant to verify whether it is a valid grant or not. the receiving device verifies the cell bus routing header cyclic redundancy check (crc-4) value in the least significant 4 bits of the cell bus routing header. it also verifies the bit interleave parity (bip-8) value from bits 24 to 31 of the last cell bus frame cycle. if either is corrupt, the cell is discarded. if kept, cells are routed to the loopback fifo, control fifo, or tx phy fifo, based on the information in its cell bus routing header. see section 10.3, cell bus routing headers.
agere systems inc. 61 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.2 cell bus frames a cell bus frame is always 16 clock cycles. the cell bus frame has three sections (request, bus cell, and grant). during the request section, which is the first clock cycle of the frame, 16 devices assert their transmission requests onto the bus. during the bus cell section, which is the next 14 clock cycles, a cell is transmitted on the cell bus. this bus cell includes the cell bus routing header, the tandem routing header, and the 52-byte body of the cell. dur- ing the grant section, which is the last clock cycle of the frame, the grant is asserted, indicating which device may transmit its cell during the next frame. also, during this last clock cycle, a parity vector is placed on the bus by the transmitting device so that error detection can be performed on the cell. figure 13 illustrates the format for the cell bus frame. figure 13. cell bus frame format (bit positions for 16-user mode) 31 16 15 0 cycle 0 u15 u14 u13 u12 u11 u10 u9 u8 u7 u6 u5 u4 u3 u2 u1 u0 cycle 1 cell bus routing header tandem routing header cycle 2 gfc/ vpi[11:8] vpi[7:0] vci[15:0] pti c l p cycle 3 payload byte 0 payload byte 1 payload byte 2 payload byte 3 cycle 4 payload byte 4 payload byte 5 payload byte 6 payload byte 7 cycle 5 payload byte 8 payload byte 9 payload byte 10 payload byte 11 cycle 6 payload byte 12 payload byte 13 payload byte 14 payload byte 15 cycle 7 payload byte 16 payload byte 17 payload byte 18 payload byte 19 cycle 8 payload byte 20 payload byte 21 payload byte 22 payload byte 23 cycle 9 payload byte 24 payload byte 25 payload byte 26 payload byte 27 cycle 10 payload byte 28 payload byte 29 payload byte 30 payload byte 31 cycle 11 payload byte 32 payload byte 33 payload byte 34 payload byte 35 cycle 12 payload byte 36 payload byte 37 payload byte 38 payload byte 39 cycle 13 payload byte 40 payload byte 41 payload byte 42 payload byte 43 cycle 14 payload byte 44 payload byte 45 payload byte 46 payload byte 47 cycle 15 bit interleave parity g p g e grant number
62 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) figure 14. cell bus frame format (bit positions for 32-user mode) 31 16 15 0 cycle 0 u15 u14 u13 u12 u11 u10 u9 u8 u7 u6 u5 u4 u3 u2 u1 u0 cycle 1 cell bus routing header tandem routing header cycle 2 gfc/ vpi[11:8] vpi[7:0] vci[15:0] pti c l p cycle 3 payload byte 0 payload byte 1 payload byte 2 payload byte 3 cycle 4 payload byte 4 payload byte 5 payload byte 6 payload byte 7 cycle 5 payload byte 8 payload byte 9 payload byte 10 payload byte 11 cycle 6 payload byte 12 payload byte 13 payload byte 14 payload byte 15 cycle 7 payload byte 16 payload byte 17 payload byte 18 payload byte 19 cycle 8 payload byte 20 payload byte 21 payload byte 22 payload byte 23 cycle 9 payload byte 24 payload byte 25 payload byte 26 payload byte 27 cycle 10 payload byte 28 payload byte 29 payload byte 30 payload byte 31 cycle 11 payload byte 32 payload byte 33 payload byte 34 payload byte 35 cycle 12 payload byte 36 payload byte 37 payload byte 38 payload byte 39 cycle 13 payload byte 40 payload byte 41 payload byte 42 payload byte 43 cycle 14 payload byte 44 payload byte 45 payload byte 46 payload byte 47 cycle 15 bit interleave parity g p g e grant number cycle 16 u31 u30 u29 u28 u27 u26 u25 u24 u23 u22 u21 u20 u19 u18 u17 u16 cycle 17 cell bus routing header tandem routing header cycle 18 gfc/ vpi[11:8] vpi[7:0] vci[15:0] pti c l p cycle 19 payload byte 0 payload byte 1 payload byte 2 payload byte 3 cycle 20 payload byte 4 payload byte 5 payload byte 6 payload byte 7 cycle 21 payload byte 8 payload byte 9 payload byte 10 payload byte 11 cycle 22 payload byte 12 payload byte 13 payload byte 14 payload byte 15 cycle 23 payload byte 16 payload byte 17 payload byte 18 payload byte 19 cycle 24 payload byte 20 payload byte 21 payload byte 22 payload byte 23 cycle 25 payload byte 24 payload byte 25 payload byte 26 payload byte 27 cycle 26 payload byte 28 payload byte 29 payload byte 30 payload byte 31 cycle 27 payload byte 32 payload byte 33 payload byte 34 payload byte 35 cycle 28 payload byte 36 payload byte 37 payload byte 38 payload byte 39 cycle 29 payload byte 40 payload byte 41 payload byte 42 payload byte 43 cycle 30 payload byte 44 payload byte 45 payload byte 46 payload byte 47 cycle 31 bit interleave parity g p g e grant number
agere systems inc. 63 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) devices on the cell bus make their requests during the first cycle of each frame. in 16-user mode, each device asserts a request every frame. in 32-user mode, each device asserts a request every two frames. in 32-user mode, devices with unit addresses 0 through 15 assert their requests during the even frames, and devices with unit addresses 16 through 31 assert their requests during the odd frames. during cycle 0 of their assigned frame, each device drives two of the 32 data bits available. the position of the two request bits for each device is based on the devices unit address. the assigned bit positions for each device are illustrated in figure 13 and figure 14 for 16-user and 32-user modes, respectively. for example, in the figures, the device with unit address 0 makes its requests using the 2 bits labeled as u0. two bits, instead of one, are used for each device so the priority of the request may be included. the priority of the request is set up using the cb_req_pr bits in the main configura- tion/control register (address 0110h). see table 59 in section 14.3, extended memory registers , for more informa- tion. during clock cycles 1 through 14, the device that was granted the bus at the end of the previous frame sends its bus cell. the bus cell sent includes the cell bus routing header, the tandem routing header, and the original utopia cell with the header error check (hec) byte removed. the hec byte is removed because the cell bus does its own error check over the complete cell using the bit interleave parity byte. the hec byte is recreated and inserted before the received cell is placed on the utopia bus. the cell bus routing header indicates the type of the cell (data, control, loopback) and its destination (single, multi- cast, broadcast). see section 10.3, cell bus routing headers, for more information on the cell bus routing header structure. the tandem routing header is configured by the user. the 32 bits of the grant section of the frame (clock cycle 15) include the bit interleave parity (bip-8) byte, the grant parity bit, the grant enable bit, and the grant number. the most significant 8 bits of the grant section of the frame is the bip-8 byte. the bip-8 byte is calculated over 54 bytes, starting with the first tandem routing header byte and ending with the last payload byte. to calculate this bit interleave parity, an exclusive-or operation is performed on the first byte of the tandem routing header and the value 11111111. the exclusive-or operation then is performed on this result and the following byte. the operation is then repeated with every successive byte through the last data byte of the payload. the resulting byte becomes the bip-8 byte of the grant section. the next 17 bits of the grant section are unused. the least significant 7 bits of the grant section are used to grant transmission requests. the grant number is located in the least significant 5 bits of the grant section and is the unit address of the device that transmits a cell during the next frame. the grant enable, bit 5, is an active-high signal that indicates if the grant is valid. finally, the grant parity, bit 6, is the odd parity check calculated over the other six grant bits.
64 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.3 cell bus routing headers the cell bus routing header gives information about the cell and its routing. there are seven different formats for cell bus routing headers. see figure 15. these headers cover broadcast, multicast, and single address routing. a t8208 device on the cell bus accepts all broadcast cells and certain multicast cells that it is configured to accept. broadcast or multicast routed cells may be data cells or control cells. the t8208 receiving device accepts single address cells with an address field in its cell bus routing header that matches the devices unit address. cells, routed as single address, may be data, control, or loopback cells. figure 15. cell bus routing headers the h field (b0 to b3) is the cell bus routing header cyclic redundancy check (crc-4) calculated over the other 12 bits (b4 to b15) of the header. it is provided for cell bus routing header error detection. when cells arrive from the cell bus, the receiving device calculates the crc-4 over the most significant 12 bits of the cell bus routing header and compares its calculation to the crc-4 value stored in the h field of the cell bus routing header. if the two do not match, the cell is discarded. multicast control cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 11 multicast net number h multicast data cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 0 multicast net number h single destination data cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 unit a ddress h single destination control cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 unit a ddress h single destination loopback cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 unit address h broadcast data cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 1 h broadcast control cell header b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 h
agere systems inc. 65 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.3.1 control cells the microprocessor connected to the t8208 may send control cells to the cell bus by writing the cell to the control cell transmit direct memory at addresses a0h to d7h (or extended memory at addresses 0900h to 0936h). after the cell is written to memory, the microprocessor sets the cntl_cell_wr bit in the main configuration/control register (address 0110h). this bit returns to zero when the cell is transmitted and memory is available to load a new control cell into the device. control cells accepted from the cell bus are routed to the control cell rx fifo. the microprocessor connected to the t8208 reads the control cell at the head of the fifo using the control cell receive direct memory at addresses 5ch to 93h (or extended memory at addresses 07fch to 0832h). after the microprocessor reads the cell, it sets the cntl_cell_rd bit in the main configuration/control register (address 0110h) to remove the cell from the head of the fifo. the microprocessor connected to the t8208 can read the cell bus routing header [15:0] and the tandem routing header [15:0] of the received control cell. the cell bus routing header [7:0] is at address 5ch and the cell bus rout- ing header [15:8] is at address 5dh. the tandem routing header [7:0] is at address 5eh and the tandem routing header [15:8] is at address 5fh. 10.3.2 data cells data cells accepted from the cell bus are routed to the tx phy fifo. from the tx phy fifo, the cell is routed to the appropriate transmit queue using the information about the cell's priority and the queue group to which it is des- tined. the priority of the cell is indicated by 2 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and atm cell header). the position of these 2 bits in the cell are user programma- ble during configuration using the prior0_sel[5:0] and prior1_sel[5:0] bits of the routing information 3 register (address 0204h). the queue group to which the cell is destined is indicated by 5 bits obtained from the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and atm cell header). the position of these 5 bits in these headers are user programmable using the mphy1_sel[5:0] and mphy2_sel[5:0] bits of the routing informa- tion 1 register (address 0200h), the mphy0_sel[5:0] bits of the routing information 2 register (address 0202h) and the mphy3_sel[5:0] and mphy4_sel[5:0] bits of the routing information 3 register (address 0214h). see tables 139, 140, 141, and 149 in section 14.3, extended memory registers. none of the priority or mphy bits are required to be adjacent. for more information on queue groups, see section 11.4, queuing.
66 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.3.3 loopback cells a loopback cell may be sent to the cell bus for diagnostic purposes. initially, the loopback cell is sent from one t8208 (device 1) to a second t8208 (device 2). the second t8208 (device 2) returns the cell to the first t8208 (device 1), or, if desired, the second t8208 (device 2) may send the cell on to one or more entirely different t8208 devices. device 2 accepts the loopback cell and replaces the most significant 12 bits of the cell bus routing header with the routing_header bits in its loopback register (address 0136h). the 12 routing_header bits in the loopback register correspond to the upper 12 bits of a single destination control cell header, a multicast control cell header, or a broadcast control cell header. to create a loopback path from device 1 to device 2, and back to device 1, coordinated control of device 1 and device 2 is needed. first, the microprocessor connected to device 2 sets up the loopback by writing the routing_header bits in the loopback register of device 2. the routing_header bits indicate a single destination con- trol cell with a unit address field for device 1. second, the microprocessor connected to device 1 writes a loopback cell to the control cell transmit direct memory (addresses a0h to d7h) of device 1. (see section 10.3.1, control cells, of this document.) the cell bus routing header of this cell is the single destination loopback type, and the unit address section of the header contains the address of device 2. to send the loopback cell, a 1' is then written to the cntl_cell_wr bit of the main configuration/control register (address 0110h). care must be taken to ensure that the routing_header bits in a t8208 device are not changed until any previously set up loopback cell has been received and retransmitted. if these bits are changed prematurely, misrouting will occur. instead of having to program the loopback register (0136h) of device 2, the tandem routing header of the incoming loopback cell (into device 2) can be used as the new cell bus routing header of the outgoing loopback cell. if the insert_cb_lpbk_hdr bit (bit 8 in register 0130h) is cleared to 0 then the t8208 device uses the tandem routing header of the incoming loopback cell as the new cell bus routing header of the outgoing loopback cell and as a result, also inserts the programmed loopback header (in register 0136h) as the tandem routing header of the out- going loopback cell. if this bit (bit 8 in register 0130h) is set to 1 the t8208 inserts the programmed loopback header (in register 0136h) as the new cell bus routing header of the loopback cell. 10.3.4 multicast routing the t8208 may be programmed to accept certain multicast data cells using the multicast memories at addresses e0h through ffh (or c00h through c1eh) and c20h through ffeh. the net numbers of accepted multicast control cells are programmed in the memory space e0h through ffh (or c00h through c1eh) and c20h through ffeh. these memory spaces hold 256 bits each. each bit represents a multicast net number from 0 to 255. note: to prevent potential multicast memory errors, these memory spaces should be cleared during the initializa- tion process. for 8-bit utopia atm mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 32 queue groups. if 64 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to phy 0, ports two and three use the mem- ory assigned to phy 1, and so on. for 16-bit utopia atm mode, the net numbers of accepted multicast data cells are programmed in the multicast number memories, which are divided among 16 queue groups. if 32 ports are used, each memory space is shared between two ports, e.g., ports zero and one use the memory assigned to phy 0, ports two and three use the mem- ory assigned to phy 1, and so on. the cell priority bits select the specific queue in the queue group to which the cell is routed. (see section 11.4, queuing). note that multicast control cells use the same multicast number memory as phy 0 multicast data cells. see table 176 in section 14.3, extended memory registers and table 53 in section 14.2, direct memory access registers, respectively. for phy mode, multicast cells are only transmitted to queue group 0, and only the phy port 0 and control cell mul- ticast direct memory at addresses e0h through ffh (or c00h through c1eh) is used. the cell priority determines the specific queue in queue group 0 to which the cell is routed. (see section 10.3.2, data cells.)
agere systems inc. 67 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.3.5 broadcast routing broadcast control cells are transmitted and received as described in section 10.3.1, control cells. the broadcast control cell bus routing header has a broadcast control cell header type. for atm mode, all phy ports receive the broadcast data cell. the cell priority bits select the specific queue in the queue group to which the cell is routed. for phy mode, if sdram is bypassed, broadcast data cells are only transmitted to queue 0. if the sdram is not bypassed, broadcast data cells are only transmitted to queue group 0, and only phy port 0 is used (although the device will take the time to try to broadcast data cells to all the ports, cells will not be stored in queue groups other than 0). 10.4 cell bus arbitration one of the t8208 devices sharing the cell bus must be configured as bus arbiter by clearing the cb_arb_sel bit in the cell bus configuration/status register (address 0130h) or by pulling the arb_en* lead low. using an arbitration algorithm, the arbiter decides the next device to transmit on the cell bus and issues the grant signals at the end of the cell bus frame. the arbiter also generates the active-low frame synchronization signal that occurs every 16 clock cycles in 16-user mode and every 32 clock cycles in 32-user mode. to grant transmission requests, the arbiter must analyze requests received during the request section of the cur- rent frame for 16-user mode or during two request cycles for 32-user mode. the arbitration algorithm used is round robin and based on the priority of the request and the last request granted. the arbiter circuitry in all t8208 devices on the cell bus will synchronize to the active arbiter on the cell bus. so, when an inactive device becomes the arbiter, it will begin sending frame synchronization signals that coincide to the clock cycle that the original arbiter would have sent its next frame synchronization signal. this prevents the new arbiter from misinterpreting random signals on its first request cycle as valid requests. the t8208 that has been configured as the bus arbiter can mask (remove) any of the active devices on the cell bus from the arbitration logic so that they will never be granted the bus. if any of the bits are set in register 12eh (en_req_low_bp[15:0]) and register 12ch (en_req_up_bp[15:0]), then the cell bus access requests from the corre- sponding unit address on the bus are enabled into the arbitration logic. if any of the bits are cleared to 0, access requests are masked and ignored by the arbitration logic.
68 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.5 cell bus monitoring every t8208 device monitors the cell bus for proper operation. the monitoring section of the t8208 checks for the presence of the read clock, the write clock, and the frame synchronization signal. the cb_wc_miss bit in the main interrupt status 1 register (address 0102h) is set when the write clock is inactive for 32 mclk cycles. likewise, the cb_rc_miss bit in the main interrupt status 1 register is set when the read clock is inactive for 32 mclk cycles. in addition, the cb_fs_miss bit in the main interrupt status 1 register is set when the frame synchronization signal is inactive for greater than 16 cell bus read clock cycles for 16-user mode or for greater than 32 read clock cycles for 32-user mode. this bit is also set when the cell bus write clock is inactive for 32 mclk cycles. when cells arrive from the cell bus, the cell bus monitoring section of the receiving device calculates the bit inter- leave parity value over the 54-byte field from the first tandem routing header byte through the final payload byte. if this calculated value does not match the value in bits 24 through 31 of the final clock cycle of the frame, the cell is discarded. the t8208 detects when a device asserts transmission requests and is not granted permission within a program- mable time period. the cb_grnt_to bit in the main interrupt status 1 register (address 0102h) is set when a device has not been granted permission to transmit within the number of frames programmed in the cb_req_to bits of the main configuration 3 register (address 0116h). 10.6 gtl+ logic for the t8208, the cell bus data, frame sync, and acknowledge signals use onboard gtl+ transceivers, and the cell bus clock signals use onboard gtl+ receivers. the gtl+ bus drivers are open drain and require terminating resistors at both ends of each line. the terminating resistor (r) may be from 40 w to 50 w and should be pulled up to 1.5 v 10% (v tt ). the actual value of the terminating resistors should be chosen to match the bus line imped- ance. figure 16a below illustrates the terminating resistors and the configuration of one gtl+ bus line. the termi- nation resistors are typically placed at the ends of the bus of the backplane. the signal rise and fall times from the transceivers are carefully controlled to minimize out-of-band signals without affecting the overall transmission rates. these controlled signal edges, in addition to proper resistive line termina- tion, minimize noise and ringing. the slew rate of the gtl+ buffers can be programmed using bits [2:0] of register 2eh. the gtl+ receiver compares its input signal to a voltage reference, cb_vref, to determine the logic level of the input. the value of the voltage reference is 2/3 v tt and is created using the voltage divider shown in figure 16b. the 1 k w resistors are 1% because the cb_vref voltage must track v tt by 1%. the 0.01 m f capacitor is a decou- pling capacitor on the cb_vref input. figure 16. gtl+ external circuitry 5-8011a (f) 5-8012a(f) a. gtl+ bus with terminating resistors b. gtl+ threshold voltage reference rr v tt v tt celxpres t8208 celxpres t8208 celxpres t8208 1 k w 1% 1 k w 1% v tt 1 k w 1% cb_vref 0.01 m f cb_vref_vss
agere systems inc. 69 advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.7 cell bus write and read clocks the read and write clocks (cb_wc* and cb_rc* pins) are supplied from an external source. the write clock should be delayed 1.5 ns to 4 ns relative to the read clock to ensure sufficient data hold time. the position of the clock source relative to the cell bus devices on the card or on connecting cards determines the actual delay that should be used. when the clock source is centrally located among the cell bus devices, a longer delay may be used. when the clock source is at either end of the cell bus devices, a shorter delay is needed. also, a higher clock fre- quency requires a shorter delay. the t8208 can generate both the read and write clocks internally for the cell bus logic, if bit 6 in register 2eh is cleared to 0 and bit 10 in register 122h is set to 1. it includes the ability to derive these clocks from several sources (pclk or mclk or pll vco frequency [twice the mclk]) and set the skew between the read and write clocks with a programmable granularity (bits 15:13 in register 122h). this feature is useful if the digital loopback (see section 10.9) is to be used when the card containing the t8208 is operated outside the system. if bit 6 in register 2eh is cleared to 0 and bit 10 in register 0122h is set to 1 , then the generated read and write cell bus clocks not only drive the internal cell bus logic of this device but also come out on pins cb_gen_rc and cb_gen_wc (pins b4 and a3, respectively) of this device which can then be used to drive the remaining devices on the backplane. note: due to the inherent propagation delay between the clocks that drive the cell bus logic of the generating device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2eh to 1 and set bit 10 in register 0122h to 1 and route these generated clocks (through a gtl+ driver) back to the cb_wc* and cb_rc* pins (pins a10 and b10, respectively). if this bit (bit 10 in register 0122h) is cleared to 0 these 2 pins, cb_gen_rc and cb_gen_wc, are inactive and are 3-stated. in this case, bit 6 in register 2eh is set to 1 to indicate that pins a10 and b10 will be receiving clocks from a different source on the board. please see registers 2eh and 0122h for more details.
70 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 10 cell bus interface (continued) 10.8 modify cell bus request priority based on rx phy fifo threshold this allows the t8208 device to modify the request priority for a cell on the cell bus, based on the rx phy fifo thresholds. this feature is useful to raise the priority of cells to avoid a situation where the queue is getting filled with low priority cells and hence the high priority cells are blocking low priority cells from being sent to the cell bus. there are two thresholds. threshold 1 to force request priority to medium and threshold 2 to force request priority to high. bit 4 in register 126h, cb_prio2_thr_en when set, enables the threshold 2. bits [3:0] in register 0126h, cb_prio2_thr, set the threshold 2. bit 12 in register 126h, cb_prio1_thr_en when set, enables the threshold 1. bits [11:8] in register 0126h, cb_prio1_thr, set the threshold 1. note: when bits 3:2 in register 0110h are set to 00 (disabled) and this feature is enabled, cells are transmitted onto the cell bus as soon as the priority medium is reached. to prevent this, either the feature needs to be disabled or cells should not be transmitted to this fifo. note: these threshold levels cannot be changed when there is data flowing through the celxpres device. 10.9 digital loopback before cell bus the digital loopback allows loopback of all cells without requiring the cell to be sent to the cell bus. the output of the cell bus output fifo is connected to the input of the cell bus input fifo internally, so that the cells do not have to go through the gtl+ buffers. the cells being received on the rx utopia should still be addressed properly with in-range vpi/vci and routing information for the device to be able to loopback the cells. bit 7 (dig_lpbk_en) in register 2eh must be set to 1 and bit 2 (gtltpdn) in register 2fh must be cleared to 0 to enable a digital loopback . cell bus request priority bits 3:2 in register 110h priority when threshold 1 is reached priority when threshold 2 is reached 00 = disabled medium high 01 = low priority medium high 10 = medium priority medium high 11 = high priority high high
agere systems inc. 71 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface for outgoing utopia cells, the tx utopia cell buffer supports 128 queues. these queues are separated into 32 queue groups, each consisting of four different priority queues as described in section 9.2.2, outgoing atm mode (cells sent by t8208). this cell buffer holds 256 outgoing cells. additional buffering is provided by an exter- nal sdram. connection to an external sdram is selected by clearing the sdram_bypass bit in the main configu- ration 1 register (address 0100h). if the sdram is not used, it is bypassed by setting the sdram_bypass bit in the main configuration 1 register at start-up. when the sdram is bypassed, the minimum number of queues that the tx utopia cell buffer can be divided into is 1 queue and the maximum number of queues is 128 queues (atm mode) or 4 queues (phy mode). the buffering available in this mode is the 256-cell internal memory (tx phy fifo) and up to 256 cells of the tx utopia cell buffer. (the two buffers are not concatenated.) the setting of the div_queue bits in the main configu- ration 2 register (address 0112h) determines the number of cell locations allocated to queues of the tx utopia cell buffer. 11.1 memory configuration the sdram interface supports from 2 mbytes to 32 mbytes of memory. this memory size is realized using 16 mbit or 64 mbit devices. table 19 below outlines the various memory configurations supported. table 19. supported memory configurations 11.2 powerup sequence the powerup sequence for the sdram must be performed manually before the sdram is enabled. using the idle state 1 and 2 registers (addresses 0420h and 0422h), the manual access state 1 and 2 registers (addresses 0424h and 0426h), and the gen_man_acc bit in the sdram control register (address 0400h), follow the powerup command sequence prescribed by the sdram manufacturer. the t8208 does not control the chip select, the clock enable, and the dqm inputs to the sdram. these signals should be externally tied to the appropriate logic level or external control signal. to manually execute sdram commands, first set up the idle values for cas*, ras*, we*, bank select (bs), and the address signals using the cas_idle, ras_idle, we_idle, bs_idle[1:0], and addr_idle[11:0] bits in the idle state 1 and 2 registers. then manually set up the value of these signals for the first sdram command using the cas_man, ras_man, we_man, bs_man[1:0], and addr_man[11:0] bits in the manual access state 1 and 2 registers. finally, write a 1 to the gen_man_acc bit in the sdram control register. writing this 1 drives the cas, ras, we*, bs, and address values (in the manual access state 1 and 2 registers) onto the associated pins for one sdram clock cycle. after the one clock cycle, these signals return to their idle state. repeat this process, making sure minimum timing between commands is met, until the powerup process has been completed. in the powerup sequence, configure the mode register of the sdram for a burst length of one and a cas latency of two or three. with a burst length of one, sequential and interleave addressing behave the same, so the sdram may be configured for either addressing mode. number of devices device memory size and data bus organization number of columns number of banks number of rows total memory 1 16 mbit, 16-bit data bus 256 2 2048 2 mbyte 2 16 mbit, 8-bit data bus 512 2 2048 4 mbyte 4 16 mbit, 4-bit data bus 1024 2 2048 8 mbyte 1 64 mbit, 16-bit data bus 256 4 4096 8 mbyte 2 64 mbit, 8-bit data bus 512 4 4096 16 mbyte 4 64 mbit, 4-bit data bus 1024 4 4096 32 mbyte
72 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) 11.3 sdram interface timing the mclk clock is the source of the sdram clock (sd_clk) from the t8208. based on the frequency of the sdram clock and the speed grade of the sdram, four timing parameters must be programmed into the sdram configu- ration register at address 0408h. these timing parameters are specified in sdram (mclk) clock cycles and are listed below: n ras inactive to cas active (ras2cas)its value may be set from two to four sdram clock cycles. n cas inactive to precharge command active (cas2pre)its value may be set from one to four sdram clock cycles. n precharge command inactive to next command active (pre2cmd)its value may be set from one to four sdram clock cycles. n cas before ras (cbr) refresh command inactive to next cbr refresh command active (ref2cmd)its value may be set to three, seven, or fifteen sdram clock cycles. actual values for these parameters are obtained from the data sheet of the sdram used. for optimum perfor- mance, these parameters should be programmed to the lowest acceptable values. the earliest time that a cas may be asserted after an ras may be obtained from the data sheet parameter that describes the minimum time from the activate command to the read/write command. three parameters affect the earliest time that a precharge command may follow a cas. for read commands, a precharge command may be issued one clock earlier than the last read data. the actual number of clock cycles depends on the cas latency needed for the device. for write commands, the earliest time that a precharge command may be issued following a cas may be obtained from the sdram data sheet parameter that describes the minimum time from the last data in to the precharge command. in addition to these two parameters, the minimum time from the activate command to the precharge command may need to be considered to obtain the value for cas2pre. if the sdram is only accessed for queuing purposes, 28 consecutive cas commands will be executed between the activate command and the precharge command, and the minimum time from the activate command to the precharge command does not need to be considered. if the microprocessor reads and writes the sdram memory, only one cas command will be executed between the activate command and the precharge command. in this case, the minimum time from the activate command to the precharge command is significant and must be considered. the minimum time from the precharge command to the next command may be obtained from the data sheet parameter that describes the minimum time from the pre- charge command to the activate command. the minimum time from the cbr refresh command to the next cbr refresh command may be obtained from the data sheet. in the t8208, the minimum time from cbr refresh to any other command is 15 sdram clock cycles. in the data sheet, the parameters may be specified in actual time units rather than clock cycles. to determine the number of clock cycles, divide the parameter value by the sdram clock period. figure 17 below illustrates these timing parameters and the number of clock cycles needed to read or write a cell using the default values for the parameters. 5-7785bf figure 17. sdram timing parameters ras (1) cbr refresh { 2 , 3, 4} ras2cas cas (1 to 28) { 1 , 2, 3, 4} cas2pre precharge (1) {3, 7, 15 } ref2cmd {1, 2 , 3, 4} pre2cmd next command single command the boxes represent the number of idle cycles between states. default values are in bold for ras2cas, cas2pre, pre2cmd, and ref2cmd. (1)
agere systems inc. 73 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) 11.4 queuing for a device configured in atm mode, up to 32 groups of queues with four priorities per group may be configured in the sdram for a total of 128 queues. therefore, the five port group address bits point to one of 32 queue groups, and the two priority bits point to one of four queues in the group. (for a description of the port group address and priority bits, see section 10.3.2, data cells.) priority bits with a value of zero represent the highest pri- ority, and those with a value of three, the lowest priority. if an atm is configured to support 32 phy ports in 8-bit utopia mode (a value of 0011 in bits 3:0 of register 0112h), each port is assigned to its associated queue group as illustrated in table 20, regardless of the value of the port_rte[127:0] bits. in this case, port 0 is assigned to queue group 0, port 1 to queue group 1, and so on. for an atm configured to support 64 phy ports in 8-bit utopia mode and 32 phy ports in 16-bit utopia mode, each queue group is shared between two ports as specified in section 9.2.2, outgoing atm mode (cells sent by t8208), and the four queues may be split in any way between the two ports using the port_rte[127:0] bits. table 21 illustrates the relationship between the queue organization and the port group address/priority bits for a device configured to support 64 phy ports in 8-bit utopia mode and 32 phy ports in 16-bit utopia mode, and whose port_rte[127:0] bits are programmed to the normal 64-port mode as described in section 9.2.2, outgoing atm mode (cells sent by t8208). see the txphy fifo routing 7, 6, 5, 4, 3, 2, 1, and 0 registers at addresses 0170h, 0172h, 0174h, 0176h, 0178h, 017ah, 017ch, and 017eh, respectively.
74 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 20. queue organization and port group address/priority bits for 32 ports in 8-bit utopia mode port number queue group queue number priority port group address bits priority bits 0 0 0 highest 00000 00 0 0 1 high 00000 01 0 0 2 low 00000 10 0 0 3 lowest 00000 11 1 1 4 highest 00001 00 1 1 5 high 00001 01 1 1 6 low 00001 10 1 1 7 lowest 00001 11 2 2 8 highest 00010 00 2 2 9 high 00010 01 2 2 10 low 00010 10 2 2 11 lowest 00010 11 3 3 12 highest 00011 00 3 3 13 high 00011 01 3 3 14 low 00011 10 3 3 15 lowest 00011 11 4 4 16 highest 00100 00 4 4 17 high 00100 01 4 4 18 low 00100 10 4 4 19 lowest 00100 11 5 5 20 highest 00101 00 5 5 21 high 00101 01 5 5 22 low 00101 10 5 5 23 lowest 00101 11 6 6 24 highest 00110 00 6 6 25 high 00110 01 6 6 26 low 00110 10 6 6 27 lowest 00110 11 7 7 28 highest 00111 00 7 7 29 high 00111 01 7 7 30 low 00111 10 7 7 31 lowest 00111 11 8 8 32 highest 01000 00 8 8 33 high 01000 01 8 8 34 low 01000 10 8 8 35 lowest 01000 11 9 9 36 highest 01001 00 9 9 37 high 01001 01 9 9 38 low 01001 10 9 9 39 lowest 01001 11
agere systems inc. 75 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 20. queue organization and port group address/priority bits for 32 ports in 8-bit utopia mode (continued) port number queue group queue number priority port group address bits priority bits 10 10 40 highest 01010 00 10 10 41 high 01010 01 10 10 42 low 01010 10 10 10 43 lowest 01010 11 11 11 44 highest 01011 00 11 11 45 high 01011 01 11 11 46 low 01011 10 11 11 47 lowest 01011 11 12 12 48 highest 01100 00 12 12 49 high 01100 01 12 12 50 low 01100 10 12 12 51 lowest 01100 11 13 13 52 highest 01101 00 13 13 53 high 01101 01 13 13 54 low 01101 10 13 13 55 lowest 01101 11 14 14 56 highest 01110 00 14 14 57 high 01110 01 14 14 58 low 01110 10 14 14 59 lowest 01110 11 15 15 60 highest 0 1111 00 15 15 61 high 01111 01 15 15 62 low 01111 10 15 15 63 lowest 01111 11 16 16 64 highest 10000 00 16 16 65 high 10000 01 16 16 66 low 10000 10 16 16 67 lowest 10000 11 17 17 68 highest 10001 00 17 17 69 high 10001 01 17 17 70 low 10001 10 17 17 71 lowest 10001 11 18 18 72 highest 10010 00 18 18 73 high 10010 01 18 18 74 low 10010 10 18 18 75 lowest 10010 11 19 19 76 highest 10011 00 19 19 77 high 10011 01 19 19 78 low 10011 10 19 19 79 lowest 10011 11 20 20 80 highest 10100 00 20 20 81 high 10100 01 20 20 82 low 10100 10 20 20 83 lowest 10100 11
76 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 20. queue organization and port group address/priority bits for 32 ports in 8-bit utopia mode (continued) port number queue group queue number priority port group address bits priority bits 21 21 84 highest 10101 00 21 21 85 high 10101 01 21 21 86 low 10101 10 21 21 87 lowest 10101 11 22 22 88 highest 10110 00 22 22 89 high 10110 01 22 22 90 low 10110 10 22 22 91 lowest 10110 11 23 23 92 highest 10111 00 23 23 93 high 10111 01 23 23 94 low 10111 10 23 23 95 lowest 10111 11 24 24 96 highest 11000 00 24 24 97 high 11000 01 24 24 98 low 11000 10 24 24 99 lowest 11000 11 25 25 100 highest 11001 00 25 25 101 high 11001 01 25 25 102 low 11001 10 25 25 103 lowest 11001 11 26 26 104 highest 11010 00 26 26 105 high 11010 01 26 26 106 low 11010 10 26 26 107 lowest 11010 11 27 27 108 highest 11011 00 27 27 109 high 11011 01 27 27 110 low 11011 10 27 27 111 lowest 11011 11 28 28 112 highest 11100 00 28 28 113 high 11100 01 28 28 114 low 11100 10 28 28 115 lowest 11100 11 29 29 116 highest 11101 00 29 29 117 high 11101 01 29 29 118 low 11101 10 29 29 119 lowest 11101 11 30 30 120 highest 11110 00 30 30 121 high 11110 01 30 30 122 low 11110 10 30 30 123 lowest 11110 11 31 31 124 highest 11111 00 31 31 125 high 11111 01 31 31 126 low 11111 10 31 31 127 lowest 11111 11
agere systems inc. 77 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 21. queue organization and port group address/priority bits for 64 ports in 8-bit utopia mode and 32 ports in 16-bit utopia mode port number queue group queue number priority port group address bits priority bits 000high 00000 00 0 0 2 low 00000 10 101high 00000 01 1 0 3 low 00000 11 214high 00001 00 2 1 6 low 00001 10 315high 00001 01 3 1 7 low 00001 11 428high 00010 00 4 2 10 low 00010 10 529high 00010 01 5 2 11 low 00010 11 6 3 12 high 00011 00 6 3 14 low 00011 10 7 3 13 high 00011 01 7 3 15 low 00011 11 8 4 16 high 00100 00 8 4 18 low 00100 10 9 4 17 high 00100 01 9 4 19 low 00100 11 10 5 20 high 00101 00 10 5 22 low 00101 10 11521high 00101 01 11523low 00101 11 12 6 24 high 00110 00 12 6 26 low 00110 10 13 6 25 high 00110 01 13 6 27 low 00110 11 14 7 28 high 00111 00 14 7 30 low 00111 10 15 7 29 high 00111 01 15 7 31 low 00111 11 16 8 32 high 01000 00 16 8 34 low 01000 10 17 8 33 high 01000 01 17 8 35 low 01000 11 18 9 36 high 01001 00 18 9 38 low 01001 10 19 9 37 high 01001 01 19 9 39 low 01001 11 20 10 40 high 01010 00 20 10 42 low 01010 10 21 10 41 high 01010 01 21 10 43 low 01010 11
78 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 21. queue organization and port group address/priority bits for 64 ports in 8-bit utopia mode and 32 ports in 16-bit utopia mode (continued) port number queue group queue number priority port group address bits priority bits 22 11 44 high 01011 00 22 11 46 low 01011 10 23 11 45 high 01011 01 23 11 47 low 01011 11 24 12 48 high 01100 00 24 12 50 low 01100 10 25 12 49 high 01100 01 25 12 51 low 01100 11 26 13 52 high 01101 00 26 13 54 low 01101 10 27 13 53 high 01101 01 27 13 55 low 01101 11 28 14 56 high 01110 00 28 14 58 low 01110 10 29 14 57 high 01110 01 29 14 59 low 01110 11 30 15 60 high 01111 00 30 15 62 low 01111 10 31 15 61 high 01111 01 31 15 63 low 01111 11 32 16 64 high 10000 00 32 16 66 low 10000 10 33 16 65 high 10000 01 33 16 67 low 10000 11 34 17 68 high 10001 00 34 17 70 low 10001 10 35 17 69 high 10001 01 35 17 71 low 10001 11 36 18 72 high 10010 00 36 18 74 low 10010 10 37 18 73 high 10010 01 37 18 75 low 10010 11 38 19 76 high 10011 00 38 19 78 low 10011 10 39 19 77 high 10011 01 39 19 79 low 10011 11 40 20 80 high 10100 00 40 20 82 low 10100 10 41 20 81 high 10100 01 41 20 83 low 10100 11
agere systems inc. 79 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) table 21. queue organization and port group address/priority bits for 64 ports in 8-bit utopia mode and 32 ports in 16-bit utopia mode (continued) port number queue group queue number priority port group address bits priority bits 42 21 84 high 10101 00 42 21 86 low 10101 10 43 21 85 high 10101 01 43 21 87 low 10101 11 44 22 88 high 10110 00 44 22 90 low 10110 10 45 22 89 high 10110 01 45 22 91 low 10110 11 46 23 92 high 10111 00 46 23 94 low 10111 10 47 23 93 high 10111 01 47 23 95 low 10111 11 48 24 96 high 11000 00 48 24 98 low 11000 10 49 24 97 high 11000 01 49 24 99 low 11000 11 50 25 100 high 11001 00 50 25 102 low 11001 10 51 25 101 high 11001 01 51 25 103 low 11001 11 52 26 104 high 11010 00 52 26 106 low 11010 10 53 26 105 high 11010 01 53 26 107 low 11010 11 54 27 108 high 11011 00 54 27 110 low 11011 10 55 27 109 high 11011 01 55 27 111 low 11011 11 56 28 112 high 11100 00 56 28 114 low 11100 10 57 28 113 high 11100 01 57 28 115 low 11100 11 58 29 116 high 11101 00 58 29 118 low 11101 10 59 29 117 high 11101 01 59 29 119 low 11101 11 60 30 120 high 11110 00 60 30 122 low 11110 10 61 30 121 high 11110 01 61 30 123 low 11110 11 62 31 124 high 11111 00 62 31 126 low 11111 10 63 31 125 high 11111 01 63 31 127 low 11111 11
80 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) of the four priority queues, the highest-priority (priority zero), lowest-delay queue may be used for constant bit rate (cbr) traffic. the other three queues, in descending order of priority, may be used for variable bit rate (vbr), avail- able bit rate (abr), and unspecified bit rate (ubr) traffic, respectively. generally, as the priority becomes lower, the queues become larger because lower-priority cells are likely to accumulate while higher-priority cells are transmit- ted. the size and location of each queue is programmable using the base_addressx[24:6] and end_addrx[24:6] bits in the queue x definition structure, shown in table 173. using these base and end address registers, the size of each queue may be programmed to a minimum of four cells and up to a maximum of 512k cells in one-cell incre- ments. each queue must be disabled during queue configuration by clearing the queuex_rd_en and queuex_wr_en bits in the queue x registers (addresses 0440h through 053eh) (shown in table 172). cells sent to write-disabled queues will be discarded. cells sent to read-disabled queues will be written into the sdram but never transmitted to the tx utopia port. read-disabled queues may be used, as large external memory, to store cells bound for the microprocessor. the microprocessor may use as many queues as required for different type cells. because the microprocessor reads only 2 bytes from the sdram per access, the cas2pre value (see section 11.3, sdram interface timing) may need to be larger than that required for the transferring of cells only. therefore, to maximize the bandwidth of the sdram for cell bus to utopia traffic, restrict microproces- sor access of the sdram to the initialization function (e.g., downloading microcode over the cell bus). when the microprocessor increments the read pointer to read the sdram, it must first write the three least signifi- cant bits (rd_pntx[8:6]) of the read pointer for the appropriate queue followed by the 16 most significant bits (rd_pntx[24:9]). this order must be followed for proper operation. all queues used for microprocessor cell recep- tion must be at least 32 cells long. (see queue x definition structure, table 173, for more information on these bits.) 11.5 sdram refresh the t8208 sdram interface performs cas before ras (cbr) refresh commands at a rate programmed in the ref_cnt bits of the refresh register (address 0410h). the value in the refresh register represents refresh cycles in sdram clock cycles. one refresh command is executed every ref_cnt clock cycles, on average, when the sdram is idle. in addition, the value programmed in the refresh lateness register (address 0412h) represents the maximum time, in programmed refresh cycles, between actual refresh cycles. if this limit is exceeded, the ref_late bit in the sdram interrupt status register (address 0402h) will be set, and if the ref_late interrupt is enabled, an interrupt will be generated. the ref_late indication is provided for diagnostic purposes and does not necessarily indicate a fatal error. bit errors in the actual cell are reported in the crc8_err_even and crc8_err_odd bits of the sdram interrupt status register.
agere systems inc. 81 advance data sheet september 2001 atm interconnect celxpres t8208 11 sdram interface (continued) 11.6 sdram throughput the sdram clock frequency must be fast enough for cell transfers, to and from the sdram, to occur without over- runs to the tx phy fifo. using the default values for ras2cas, cas2pre, and pre2cmd, thirty-five clock cycles are required to transfer one cell (56 bytes) into or out of the sdram. the assumed efficiency rate is 90%. therefore, the number of cells per second that can be read or written into the sdram is calculated using the following equa- tion: cell rate = (f mclk /35 cycles per cell x 90%) where f mclk is the frequency of the sdram clock. the maximum utopia and cell bus bandwidths must be calculated to ensure that the sdram clock frequency supports these bandwidths. for example, assume that the total bandwidth on the utopia bus is 64 mbits/s and that the cell bus clock rate is 33 mhz. the maximum number of cells per second that the cell bus can send is: = 2.06 mcells per second. on the utopia port, the total number of cells that can be sent is: = 151 kcells per second. thus, the total number of cells per second from the cell bus and to the utopia bus is 2.21 mcells per second. for the cell rate equation above, the required sdram clock frequency is: * 35 cycles per cell = 86 mhz. this is a worst-case example and assumes that all potential cells on the cell bus are going to this one device. the sdram frequency calculation produces a lower frequency if the actual system characteristics are considered and if the distribution of cells is controlled. 33 mhz 16 cycles per cell --------------------------------------------- - 64 mbits/s 53 bytes per cell 8 bits per byte --------------------------------------------------------------------------------------- 2.21 mcells per second 0.9 -------------------------------------------------------------
82 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 12 traffic management 12.1 cell loss priority (clp) to avoid congestion, cells with their clp bit set may be automatically discarded upon reception at the tx phy fifo or upon reception at a queue in the sdram. the cells are discarded if the tx phy fifo or sdram queue is filled beyond the programmed limit and this feature is enabled. for the tx phy fifo, this limit is programmed in the clp_fill_limit bits of the main configuration/control register (address 0110h). the feature is enabled when the cell_drop_en bit in the main configuration/control register (address 0110h) is set. for the sdram queues, this limit is programmed for each queue (x) in the clp_fillx[24:9] and clp_fillx[8:6] bits in table 173. the feature is enabled when the queuex_clp_en bit in the queue x registers (address 0440h through 053eh) is set. when a received cell exceeds the clp fill level for a queue, the t8208 sets the corresponding queuex_clp_lim status bit in the queue x registers. if the fill level is set to zero, the corresponding queuex_clp_lim bit is set by the first received cell for the queue. any fill greater than zero has an inherent inaccuracy of seven cells; therefore, a fill limit of eight or less is not meaningful. the number of cells in each queue may be determined by reading the value of the read and write pointers for the specific queue. 12.2 forward explicit congestion notification (fecn) the t8208 supports fecn for data cells using the explicit forward congestion indication (efci) bit in the cell header pti. if enabled, fecn indicates cells that have encountered congestion by setting their efci bit. the t8208 sets the efci bit in cells that leave a queue that is filled beyond the limit programmed in the fecn_fillx[24:9] and fecn_fillx[8:6] bits. the t8208 only sets the efci bit in cells when the function is enabled by the queuex_fecn_en bit in the queue x registers (address 0440h through 053eh). when a received cell exceeds the fecn fill level for a queue, the t8208 sets the corresponding queuex_fecn_lim status bit in the queue x registers. if the fill level is set to zero, the corresponding queuex_fecn_lim bit is set by the first received cell for the queue. any fill greater than zero has an inherent inaccuracy of seven cells; therefore, a fill limit of eight or less is not mean- ingful. the number of cells in each queue may be determined by reading the value of the read and write pointers for the specific queue.
agere systems inc. 83 advance data sheet september 2001 atm interconnect celxpres t8208 12 traffic management (continued) 12.3 partial packet discard (ppd) partial packet discard (ppd) is accomplished through the cooperation of the t8208 (source), which places the cell on the cell bus and the t8208 (destination), which receives the cell from the bus. the source t8208 uses its trans- lation ram to place a unique id (ppd pointer) and ppd enable bit in the cell for each aal5 connection. the ppd pointer and ppd enable bit may consist of any bit in the first 64 bits of the bus cell (cell bus routing header, tandem routing header, and atm cell header) and are created at connection establishment. the destination t8208 uses the ppd state memory (address 1000h to 13feh) to track the state of aal5 virtual channels for partial packet discard. each bit in the memory represents one of 8192 potential aal5 virtual channels. when the virtual channel connection is initially established, the bit in ppd state memory pointed to by the ppd pointer should have been cleared. when a cell that has its ppd enabled is discarded, the bit pointed to by the ppd pointer becomes set. once this bit is set, successive cells with the same ppd pointer will be discarded until the last cell is received. the last cell is identified using the sdu-type bit in the pti of the cell header. when the last cell of the packet is received, the virtual channel's corresponding bit in the ppd state memory is automatically cleared, and the last cell is transmitted. the ppd_en_sel[5:0] bits in the ppd information 1 register specify which of the bus cell's first 64 bits (cell bus rout- ing header, tandem routing header, and atm cell header) enable ppd. ppd is enabled when the associated bit in the headers is one. the partial packet discard bits specify which of the bus cell's first 64 bits are used to create the ppd pointer. these pointer bits are ppd_pnt0_sel[5:0] through ppd_pnt12_sel[5:0] in the ppd information 1 through 7 registers (addresses 0206h through 0212h). when an aal5 virtual channel connection is initially estab- lished, its ppd bit in the ppd state memory can be cleared using the write_pul, write_val, and write_addr bits in the ppd memory write register at address 0418h.
84 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 13 jtag test access port a 5-pin test access port, consisting of the jtag_tclk, jtag_tms, jtag_tdi, jtag_tdo, and jtag_trst signals, provides the standard interface to the test logic. the jtag_trst signal is active-low and resets the jtag circuitry. when jtag_trst is high, the jtag interface is enabled. if the jtag port is not used, jtag_trst should be tied low. jtag may be used only to test the inputs, outputs, and their connection to the printed-wiring board. in jtag, serial bit patterns are shifted into the device through the jtag_tdi pin, and the results can be observed at the i/o and at the corresponding jtag serial output, jtag_tdo. since this jtag conforms to the jtag standard, the jtag_tdi and jtag_tdo may be linked to the jtag port of other devices for systemic testing. the boundary-scan description lan- guage may be found on the agere website. 13.1 instruction register the instruction register (ir) is 3 bits in length. the instructions are defined in table 22. table 22. instruction register instruction binary code description extest 000 places the boundary-scan register in extest mode. sample 001 places the boundary-scan register in sample mode. highz 010 places the boundary-scan register in highz mode. runbist 100 places the boundary-scan register in runbist mode. idcode 101 places the boundary-scan register in idcode mode. bypass 011, 110, 111 places the bypass register in the scan chain.
agere systems inc. 85 advance data sheet september 2001 atm interconnect celxpres t8208 13 jtag test access port (continued) 13.2 boundary-scan register the boundary-scan register (bsr) is 245 bits in length. table 23 gives descriptions of each cell in the boundary- scan chain beginning with the least significant bit. table 23. boundary-scan register descriptions boundary-scan register bit name pin name description 0 tr_d_oe tr_d(0:7) are inputs when tr_d_oe = 0. 1 tr_cont_oe tr_oe_n, tr_we_n, tr_a(17:0), and tr_cs(1:0) are high impedance when tr_cont_oe = 0. 2 u_rxclav0_oe u_rxclv0 is an input when u_rxclav0_oe = 0. 3 u_rxenb0_oe u_rxenb(0) is an input when u_rxenb0_oe = 0. 4 u_rxenb_oe u_rxenb(1:3) are inputs when u_rxenb_oe = 0. 5 u_rxaddr_oe u_rxadd(0:4) are inputs when u_rxaddr_oe = 0. 6 u_rxclk_oe u_rxclk is an input when u_rxclk_oe = 0. 7 gpio_oe(7) gpio(7) is an input when gpio_oe(7) = 0. 8 gpio_oe(6) gpio(6) is an input when gpio_oe(6) = 0. 9 gpio_oe(5) gpio(5) is an input when gpio_oe(5) = 0. 10 gpio_oe(4) gpio(4) is an input when gpio_oe(4) = 0. 11 gpio_oe(3) gpio(3) is an input when gpio_oe(3) = 0. 12 gpio_oe(2) gpio(2) is an input when gpio_oe(2) = 0. 13 gpio_oe(1) gpio(1) is an input when gpio_oe(1) = 0. 14 gpio_oe(0) gpio(0) is an input when gpio_oe(0) = 0. 15 d_oe d(7:0) are inputs when d_oe = 0. 16 cko_oe cko is high impedance when cko_oe = 0. 17 rdy_dtack_n_oe rdydtack is high impedance when rdy_dtack_n_oe = 0. 18 devhiz_n_high_driv e int_irq, sd_a(11:0), sd_bs(1:0), sd_cas_n, sd_ras_n, and sd_we_n are high impedance when devhiz_n_high_drive = 0. 19 u_shr_gnt_oe u_shr_gnt(0:1) are inputs when u_shr_gnt_oe = 0. 20 u_txdata_oe u_txdat(15:0) are high impedance when u_txdata_oe = 0. 21 u_txprty_oe u_txprty is an input when u_txprty_oe = 0. 22 u_txsoc_oe u_txsoc is high impedance when u_txsoc_oe = 0. 23 u_txclk_oe u_txclk is an input when u_txclk_oe = 0. 24 u_txaddr_oe u_txadd(4:0) are inputs when u_txaddr_oe = 0. 25 u_txenb_oe u_txenb(3:1) are high impedance when u_txenb_oe = 0. 26 u_txenb0_oe u_txenb0 is an input when u_txenb0_oe = 0. 27 u_txclav0_oe u_txclv0 is an input when u_txclav0_oe = 0.
86 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 13 jtag test access port (continued) table 23 . boundary-scan register descriptions (continued) boundary-scan register bit name pin name description 28 sd_clk_oe sd_clk is an input when sd_clk_oe = 0. 29 sd_d_oe sd_d(15:0) are inputs when sd_d_oe = 0. 30 cb_gen_oe cb_gen_rc and cb_gen_wc are inputs when cb_gen_oe = 0. 31 u_shr_req_oe u_shr_req(0:3) are inputs when u_shr_req_oe = 0. 32-39 tr_d(0:7) tr_d[0:7] bidirectional. 40-41 tr_cs(0:1) tr_cs*[0:1] 3-statable output. 42 tr_oe_n tr_oe* 3-statable output. 43 tr_we_n tr_we* 3-statable output. 44-61 tr_a(0:17) tr_a[0:17] 3-statable output. 62 u_rxclv0 u_rxclav[0] bidirectional. 63-65 u_rxclv(1:3) u_rxclav[1:3] input. 66 u_rxenb(0) u_rxenb*[0] bidirectional. 67-69 u_rxenb(1:3) u_rxenb*[1:3] bidirectional. 70-74 u_rxadd(0:4) u_rxaddr[0:4] bidirectional. 75 u_rxclk t1 bidirectional. 76 u_rxsoc u_rxsoc input. 77 u_rxprty u_rxprty input. 78-93 u_rxdat(0:15) u_rxdata[0:15] input. 94 gpio(7) gpio[7] bidirectional. 95 gpio(6) gpio[6] bidirectional. 96 gpio(5) gpio[5] bidirectional. 97 gpio(4) gpio[4] bidirectional. 98 gpio(3) gpio[3] bidirectional. 99 gpio(2) gpio[2] bidirectional. 100 gpio(1) gpio[1] bidirectional. 101 gpio(0) gpio[0] bidirectional. 102-109 a(7:0) a[7:1] a[0]/ale input. 110-117 d(7:0) d[7:0] bidirectional. 118 cko cko 3-statable output. 119 ckoe cko_e input. 120 rdydtack rdy_dtack* 3-statable output. 121 int_irq int_irq* 3-statable output. 122 sel_n sel* input.
agere systems inc. 87 advance data sheet september 2001 atm interconnect celxpres t8208 13 jtag test access port (continued) table 23 . boundary-scan register descriptions (continued) boundary-scan register bit name pin name description 123 wr_n wr*_ds* input. 124 rd_wr_n rd*_rw* input. 125 moto mot_sel input. 126 mux mux input. 127 reset_n reset* input. 128-129 u_shr_gnt(0:1) u_shr_gnt(0:1) bidirectional. 130-145 u_txdat(15:0) u_txdata[15:0] 3-statable output. 146 u_txprty u_txprty bidirectional. 147 u_txsoc u_txsoc 3-statable output. 148 u_txclk u_txclk bidirectional. 149-153 u_txadd(4:0) u_txaddr[4:0] bidirectional. 154-156 u_txenb(3:1) u_txenb*[3:1] 3-statable output. 157 u_txenb0 u_txenb*[0] bidirectional. 158-160 u_txclv(3:1) u_txclav[3:1] input. 161 u_txclv0 u_txclav[0] bidirectional. 162-173 sd_a(11:0) sd_a[11:0] 3-statable output. 174 sd_clk sd_clk bidirectional. 175-176 sd_bs(1:0) sd_bs[1:0] 3-statable output. 177 sd_ras_n sd_ras* 3-statable output. 178 sd_cas_n sd_cas* 3-statable output. 179 sd_we_n sd_we* 3-statable output. 180-195 sd_d(15:0) sd_d[15:0] bidirectional. 196-200 ua_n(4:0) ua*[4:0] input. 201 enarb arb_enb* input. 202 cb_disbl cb_disable* input. 203 cb_ack_n cb_ack* bidirectional. 204 cb_f_n cb_fs* bidirectional. 205-220 cb_d_n(0:15) cb_d*[0:15] bidirectional. 221 cb_wc_n cb_wc* input. 222 cb_rc_n cb_rc* input. 223-238 cb_d_n(16:31) cb_d*[16:31] bidirectional. 239 cb_gen_rc_n cb_gen_rc* bidirectional. 240 cb_gen_wc_n cb_gen_wc* bidirectional. 241-244 u_shr_req(0:3) u_shr_req(0:3) bidirectional.
88 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers the t8208 has two distinct memory spaces: the direct memory access registers and the extended memory regis- ters. the direct memory access registers are directly addressed 8-bit (byte) registers and are mapped between addresses 00h and ffh. the extended memory registers are indirectly addressed and mapped between addresses 0100h and 3fffffeh. the extended memory registers are mapped into three major blocks: the main registers, the utopia registers, and the sdram registers. they contain the sdram memory, the translation ram, internal memories, and the device's configuration, status, and control registers. extended memory registers are 16 bits wide, and all accesses to the extended memory registers are executed internally as 16 bits. direct memory access registers are located in section 14.2, direct memory access registers, and extended memory registers are located in section 14.3, extended memory registers. 14.1 register types table 24. register map read/write (rw): these registers may be written or read. read only (ro): these registers may only be read. read-only latch (rol): the read-only latch is used for interrupt status registers. reading a read-only latch register has no effect on the contents. to clear a bit set in an rol register, a one must be written to the bit. writing a zero to the bit has no effect. if the corresponding interrupt enable bit is set, an interrupt will be continuously generated until the bit in the rol register is cleared. write only (wo): these registers may only be written. the write only registers in the t8208 are a pulse type. when they are written to one, they generate a pulse internally for one clock cycle and then return to zero. register name address (h) reference page direct configuration/control register (dccr) 28h 93 interrupt service request (isreq) 29h 94 mclk pll configuration 0 (mpllcf0) 2ah 94 mclk pll configuration 1 (mpllcf1) 2bh 95 gtl+ slew rate configuration (gtlsrcf) 2eh 95 gtl+ control (gtlcntrl) 2fh 96 extended memory address 1 (little endian) (ema1_le) 30h 97 extended memory address 2 (little endian) (ema2_le) 31h 97 extended memory address 3 (little endian) (ema3_le) 32h 97 extended memory address 4 (little endian) (ema4_le) 33h 97 extended memory access (little endian) (ema_le) 34h 97 extended memory data low (little endian) (emdl_le) 36h 98 extended memory data high (little endian) (emdh_le) 37h 98 extended memory address 4 (big endian) (ema4_be) 30h 99 extended memory address 3 (big endian) (ema3_be) 31h 99 extended memory address 2 (big endian) (ema2_be) 32h 99 extended memory address 1 (big endian) (ema1_be) 33h 99 extended memory access (big endian) (ema_be) 34h 100 extended memory data high (big endian) (emdh_be) 36h 100 extended memory data low (big endian) (emdl_be) 37h 100 gpio output enable (gpio_oe) 39h 101 gpio output value (gpio_ov) 3bh 101 gpio input value (gpio_iv) 3dh 101 control cell receive direct memory (ccrxdm) 5ch to 93h 102 control cell transmit direct memory (cctxdm) a0h to d7h 102 phy port 0 and control cells multicast direct memory (pp0mdm) e0h to ffh 103
agere systems inc. 89 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 24. register map (continued) register name address (h) reference page main configuration 1 (mcf1) 0100h 104 main interrupt status 1 (mis1) 0102h 105 main interrupt enable 1 (mie1) 0104h 106 tx utopia clock configuration (txuccf) 010ch 107 rx utopia clock configuration (rxuccf) 010eh 108 main configuration/control (mcfct) 0110h 109 main configuration 2 (mcf2) 0112h 110 utopia configuration (ucf) 0114h 113 main configuration 3 (mcf3) 0116h 113 utopia configuration 5 (ucf5) 0118h 114 utopia configuration 4 (ucf4) 011ah 114 utopia configuration 3 (ucf3) 011ch 114 utopia configuration 2 (ucf2) 011eh 114 extended lut control (elutcn) 0120h 115 generated cell bus clocks control register (gcbccr) 0122h 116 rx phy fifo thresholds to change cell bus request priority (rxpftcrp) 0126h 118 enable request on upper backplane (erub) 012ch 119 enable request on lower backplane (erlb) 012eh 119 cell bus configuration/status (cbcfs) 0130h 120 main interrupt status 2 (mis2) 0132h 121 main interrupt enable 2 (mie2) 0134h 122 loopback (lb) 0136h 122 extended lut configuration (elutcf) 0138h 122 misrouted cell lut 3 (mlut3) 013ch 123 misrouted cell lut 2 (mlut2) 013eh 123 misrouted cell lut 1 (mlut1) 0140h 123 misrouted cell lut 0 (mlut0) 0142h 123 misrouted cell lut 4 (mlut4) 0144h 124 misrouted cell header high (mchh) 0146h 124 misrouted cell header low (mchl) 0148h 124 hec interrupt status 3 (his3) 0300h 125 hec interrupt status 2 (his2) 0302h 125 hec interrupt status 1 (his1) 0304h 125 hec interrupt status 0 (his0) 0306h 125 hec interrupt enable 3 (hie3) 0308h 126 hec interrupt enable 2 (hie2) 030ah 126 hec interrupt enable 1 (hie1) 030ch 126 hec interrupt enable 0 (hie0) 030eh 126 hec interrupt enable 3 (hie3) 0308h 126 hec interrupt enable 2 (hie2) 030ah 126 hec interrupt enable 1 (hie1) 030ch 126 hec interrupt enable 0 (hie0) 030eh 126 lut interrupt service request 3 (lutisr3) 0310h 127 lut interrupt service request 2 (lutisr2) 0312h 127 lut interrupt service request 1 (lutisr1) 0314h 127 lut interrupt service request 0 (lutisr0) 0316h 127
90 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 24. register map (continued) register name address (h) reference page lut x configuration/status (lutxcfs) 0320h to 039eh 128 master queue 7 (mq7) 0150h 130 master queue 6 (mq6) 0152h 130 master queue 5 (mq5) 0154h 130 master queue 4 (mq4) 0156h 131 master queue 3 (mq3) 0158h 131 master queue 2 (mq2) 015ah 131 master queue 1 (mq1) 015ch 132 master queue 0 (mq0) 015eh 132 slave queue 7 (sq7) 0160h 133 slave queue 6 (sq6) 0162h 133 slave queue 5 (sq5) 0164h 134 slave queue 4 (sq4) 0166h 134 slave queue 3 (sq3) 0168h 134 slave queue 2 (sq2) 016ah 135 slave queue 1 (sq1) 016ch 135 slave queue 0 (sq0) 016eh 135 tx phy fifo routing 7 (txpfr7) 0170h 136 tx phy fifo routing 6 (txpfr6) 0172h 137 tx phy fifo routing 5 (txpfr5) 0174h 138 tx phy fifo routing 4 (txpfr4) 0176h 139 tx phy fifo routing 3 (txpfr3) 0178h 140 tx phy fifo routing 2 (txpfr2) 017ah 141 tx phy fifo routing 1 (txpfr1) 017ch 142 tx phy fifo routing 0 (txpfr0) 017eh 143 global bypass sdram control register (gbscr) 01b0h 144 bypass sdram service request register (bssr) 01beh 145 bypass sdram queue interrupt status register 0 (bsqisr0) 01c0h 147 bypass sdram queue interrupt status register 1 (bsqisr1) 01c2h 148 bypass sdram queue interrupt status register 2 (bsqisr2) 01c4h 149 bypass sdram queue interrupt status register 3 (bsqisr3) 01c6h 150 bypass sdram queue interrupt status register 4 (bsqisr4) 01c8h 151 bypass sdram queue interrupt status register 5 (bsqisr5) 01cah 152 bypass sdram queue interrupt status register 6 (bsqisr6) 01cch 153 bypass sdram queue interrupt status register 7 (bsqisr7) 01ceh 154 bypass sdram queue interrupt status register 8 (bsqisr8) 01d0h 155 bypass sdram queue interrupt status register 9 (bsqisr9) 01d2h 156 bypass sdram queue interrupt status register 10 (bsqisr10) 01d4h 157 bypass sdram queue interrupt status register 11 (bsqisr11) 01d6h 158 bypass sdram queue interrupt status register 12 (bsqisr12) 01d8h 159 bypass sdram queue interrupt status register 13 (bsqisr13) 01dah 160 bypass sdram queue interrupt status register 14 (bsqisr14) 01dch 161 bypass sdram queue interrupt status register 15 (bsqisr15) 01deh 162
agere systems inc. 91 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 24. register map (continued) register name address (h) reference page routing information 1 (ri1) 0200h 163 routing information 2 (ri2) 0202h 164 routing information 3 (ri3) 0204h 165 ppd information 1 (ppdi1) 0206h 166 ppd information 2 (ppdi2) 0208h 167 ppd information 3 (ppdi3) 020ah 168 ppd information 4 (ppdi4) 020ch 169 ppd information 5 (ppdi5) 020eh 170 ppd information 6 (ppdi6) 0210h 171 ppd information 7 (ppdi7) 0212h 172 routing information 4 (ri4) 0214h 173 ppd memory write (ppdmw) 0418h 174 phy port x transmit count structure (ppxtxcnt) 0600h to 06feh 175 phy port x receive count structure (ppxrxcnt) 4000h to 40feh 176 phy port x configuration structure (ppxcf) 4200h to 42feh 176 sdram control (sct) 0400h 179 sdram interrupt status (sis) 0402h 179 sdram interrupt enable (sie) 0404h 179 sdram configuration (scf) 0408h 180 refresh (rfrsh) 0410h 181 refresh lateness (rfrshl) 0412h 181 idle state 1 (is1) 0420h 181 idle state 2 (is2) 0422h 181 manual access state 1 (mas1) 0424h 182 manual access state 2 (mas2) 0426h 182 sdram interrupt service request 7 (sisr7) 0430h 183 sdram interrupt service request 6 (sisr6) 0432h 183 sdram interrupt service request 5 (sisr5) 0434h 183 sdram interrupt service request 4 (sisr4) 0436h 183 sdram interrupt service request 3 (sisr3) 0438h 183 sdram interrupt service request 2 (sisr2) 043ah 184 sdram interrupt service request 1 (sisr1) 043ch 184 sdram interrupt service request 0 (sisr0) 043eh 184 queue x (qx) 0440h to 053eh 185 queue x definition structure (qxdef) 2000h to 2ffeh 187 control cell receive extended memory (ccrxem) 07fch to 0832h 190 control cell transmit extended memory (cctxem) 0900h to 0936h 190 phy port 0 and control cells multicast extended memory (pp0mem) 0c00h to 0c1eh 191 phy port x multicast memory (ppxmm) 0c20h to 0ffeh 192 ppd memory (ppdm) 1000h to 13feh 193 queue x dropped cell count (qxdcc) 3000h to 31feh 194 translation ram memory (tram) 100000h to 17fffeh 197 sdram (sdram) 2000000h to 3fffffeh 197
92 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2 direct memory access registers the direct memory access registers are the only registers that can be directly addressed. these registers provide some status and initial control of the device. in addition, the direct memory access register set includes some extended memory access registers, which are used to indirectly access the extended memory registers. all unde- fined addresses in the direct memory access registers memory map, 00h to ffh, are reserved and should not be accessed. table 25. identification 0 (idnt0) (00h) table 26. identification 1 (idnt1) (01h) table 27. identification 2 (idnt2) (02h) 1. rn represents the current revision number of the device. name bit pos. type reset description device id 0 7:0 ro 4fh device identification 0. name bit pos. type reset description device id 1 7:0 ro 08h device identification 1. name bit pos. type reset description revision 7:0 ro rn 1 revision number.
agere systems inc. 93 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 28. direct configuration/control register (dccr) (28h) name bit pos. type reset description cyc_per_acc 0 rw 0 cycles per access. this bit is used to indicate the number of cycles per read/write to the translation ram. 0 = 2 mclk cycles. 1 = 3 mclk cycles. srst_reg* 1 rw 0 software reset main registers. a logic level zero on this bit resets the main registers only. the direct memory access registers (including this one) are not affected by this reset. this bit must be 0 while the mclk pll configuration 0 and 1 registers are being modified. active- low. srst* 2 rw 0 software reset . a logic level zero on this bit resets the entire device except the direct memory registers and the main registers. this bit must be 0 while the mclk pll configuration 0 and 1 registers are being modified and clocks are not present. active-low. reserved 3 ro 0 reserved. this bit must be programmed to 1. rplc_gfc 4 rw 0 replace gfc. if this bit is 1 and the device is in uni mode, the gfc field of incoming cells will be replaced during a vpi-vci translation. if this bit is 0 and the device is in uni mode, the gfc field will be left untouched. when the device is in nni mode or when a vpi only trans- lation is performed, this bit has no effect. big_end 5 rw 0 big endian. if this bit is 0, register fields in the direct address space, 30h to 37h, will be in little-endian format. if 1, fields in the direct address space, 30h to 37h, will be in big-endian format. reserved 7:6 rw 0 reserved. these bits must be written to 0.
94 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 29. interrupt service request (isreq) (29h) table 30. mclk pll configuration 0 (mpllcf0) (2ah) name bit pos. type reset description reserved 0 ro 0 reserved. int_serv_mainreg 1 ro 0 interrupt service request for main registers. when this bit is 1, an interrupt in the main register group of the extended memory regis- ters needs servicing. the control cell sent and control cell available status bits do not affect this bit. only enabled interrupts will cause this bit to become set. int_serv_sdramreg 2 ro 0 interrupt service request for sdram registers. when this bit is 1, an interrupt in the sdram register group of the extended mem- ory registers needs servicing. only enabled interrupts will cause this bit to become set. int_serv_utopiareg 3 ro 0 interrupt service request for utopia registers. when this bit is 1, an interrupt in the utopia register group of the extended mem- ory registers needs servicing. only enabled interrupts will cause this bit to become set. int_serv _sdrambypreg 4ro 0 interrupt service request for sdram bypass registers. when this bit is 1, an interrupt in the sdram bypass register group of the extended memory registers needs servicing. only enabled interrupts will cause this bit to become set. ctrl_cell_sent_sr 5 ro 0 control cell sent interrupt service request. when this bit is 1, the control cell sent interrupt in the main interrupt status 1 register needs servicing. the corresponding interrupt does not need to be enabled for this bit to become set. ctrl_cell_av_sr 6 ro 0 control cell available interrupt service request. when this bit is 1, the control cell available interrupt in the main interrupt status 1 register needs servicing. the corresponding interrupt does not need to be enabled for this bit to become set. reserved 7 ro 0 reserved. name bit pos. type reset description lf[3:0] 3:0 rw 0 loop filter. see section 5, pll configuration, for information on these bits. reserved 5:4 ro 0 reserved. bypb 6 rw 0 bypass pll. if this bit is 0, the pll is bypassed. if 1, the output of the pll supplies mclk. pllen 7 rw 0 pll enable. if this bit is 1, the pll is enabled. if 0, the pll is disabled.
agere systems inc. 95 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 31. mclk pll configuration 1 (mpllcf1) (2bh) table 32. gtl+ slew rate configuration (gtlsrcf) (2eh) name bit pos. type reset description pll_m[4:0] 4:0 rw 0 pll m count value. see section 5, pll configuration, for information on these bits. pll_n[2:0] 7:5 rw 0 pll n count value. see section 5, pll configuration, for information on these bits. name bit pos. type reset description slew_rate[2:0] 2:0 rw 4h gtl+ slew rate control [2:0]. the slew rates of the gtl+ (cell bus) output signals are controlled by these bits. the mini- mum slew rate is 0.9 ns and the maximum slew rate is 3.3 ns. 000 = fastest slew rate 001 010 011 = nominal slew rate (on fast side) 100 = nominal slew rate (on slow side) 101 110 111 = slowest slew rate reserved 3 rw 1 reserved. program to 1. reserved 5:4 rw 0 reserved. program to 0. select_gtl_clocks 6 rw 1 select gtl+ clocks. when this bit is cleared to 0, the cell bus clocks that clock the internal cell bus interface and cell bus circuitry are no longer sourced from the gtl+ input (pins a10 and b10) but rather from the generated clocks (pins a3 and b4), if they are enabled (bit 10 in 0122h = 1). if these generated clocks are disabled (bit 10 in 0122h = 0), then pins a3 and b4 become 3-stated. when this bit is set to 1 , the t8208 will receive the cell bus clocks from the gtl+ pins a10 and b10. note: due to the inherent propagation delay between the clocks that drive the cell bus logic of the generating device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2eh to 1 and set bit 10 in register 0122h to 1 and route these generated clocks (through a gtl+ driver) back to the cb_wc* and cb_rc* pins (pins a10 and b10, respectively). dig_lpbk_en 7 rw 0 digital loopback enable. this bit must be set to 1 and bit 2 (gtltpdn) of register 2fh must be cleared to 0 to enable a digital loopback (loopback before the cell bus). the digital loop- back allows loopback of all cells without requiring the cell to be sent to the cell bus. the output of the cell bus output fifo is connected to the input of the cell bus input fifo internally, so that the cells do not have to go through the gtl+ buffers. the cells being received on the rx utopia should still be addressed properly with the in-range vpi/vci and routing infor- mation for the device to be able to loopback the cells. when this bit is cleared to 0, there is no digital loopback.
96 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 33. gtl+ control (gtlcntrl) (2fh) name bit pos. type reset description reserved 0 r 1 reserved. program to 1. gtlrpdn 1 rw 1 gtl+ receive powerdown. when this bit is cleared to 0, the gtl+ receivers on the cell bus pins are powered down. under this condition, no cells can be received from the backplane. when this bit is set to 1, the gtl+ receivers are powered up and cells are received from the backplane. gtltpdn 2 rw 1 gtl+ transmit powerdown. when this bit is cleared to 0, the gtl+ transmitters on the cell bus pins are powered down. under this condition, no cells can be transmitted to the back- plane. when this bit is set to 1, the gtl+ transmitters are powered up and cells are transmitted to the backplane. reserved 4:3 r 0 reserved. program to 0. reserved 5 r 1 reserved. program to 1. reserved 7:6 r 0 reserved. program to 0.
agere systems inc. 97 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2.1 little-endian format (big_end = 0) for extended memory access registers 30h37h table 34. extended memory address 1 (little endian) (ema1_le) (30h) table 35. extended memory address 2 (little endian) (ema2_le) (31h) table 36. extended memory address 3 (little endian) (ema3_le) (32h) table 37. extended memory address 4 (little endian) (ema4_le) (33h) table 38. extended memory access (little endian) (ema_le) (34h) name bit pos. type reset description reserved 4:0 ro 0 reserved. ext_a[8:6] 7:5 rw 0 extended access address [8:6]. this extended access register points to words. name bit pos. type reset description ext_a[16:9] 7:0 rw 0 extended access address [16:9]. this extended access register points to words. name bit pos. type reset description ext_a[24:17] 7:0 rw 0 extended access address [24:17]. this extended access register points to words. name bit pos. type reset description ext_a[25] 0 rw 0 extended access address [25]. this extended access register points to words. reserved 7:1 ro 0 reserved. name bit pos. type reset description ext_a[5:1] 4:0 rw 0 extended access address [5:1]. this extended access register points to words. ext_a[0] is hardwired to 0. ext_we[1:0] 6:5 rw 0 extended access write enable. these bits are active-high write enables for word accesses. if both bits are low, a read is performed. if ext_we[1] is high, the contents of ext_d[15:8] is written, and if ext_we[0] is high, the contents of ext_d[7:0] is written. if both bits are high, both data bytes are written. ext_strt_acc 7 rw 0 start access to extended memory. write a 1' to this bit to start the access to the extended memory registers. this bit is automatically cleared when the access is complete.
98 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 39. extended memory data low (little endian) (emdl_le) (36h) table 40. extended memory data high (little endian) (emdh_le) (37h) name bit pos. type reset description ext_d[7:0] 7:0 rw 0 extended access data low. the least significant byte of data to be written to extended memory is written here before the extended write begins. the least significant byte of data read from extended memory is available here after the extended read is complete. name bit pos. type reset description ext_d[15:8] 7:0 rw 0 extended access data high. the most significant byte of data to be written to extended memory is written here before the extended write begins. the most significant byte of data read from extended memory is available here after the extended read is complete.
agere systems inc. 99 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2.2 big-endian format (big_end = 1) for extended memory access registers 30h37h table 41. extended memory address 4 (big endian) (ema4_be) (30h) table 42. extended memory address 3 (big endian) (ema3_be) (31h) table 43. extended memory address 2 (big endian) (ema2_be) (32h) table 44. extended memory address 1 (big endian) (ema1_be) (33h) name bit pos. type reset description ext_a[25] 0 rw 0 extended access address [25]. this extended access register points to words. reserved 7:1 ro 0 reserved. name bit pos. type reset description ext_a[24:17] 7:0 rw 0 extended access address [24:17]. this extended access register points to words. name bit pos. type reset description ext_a[16:9] 7:0 rw 0 extended access address [16:9]. this extended access register points to words. name bit pos. type reset description reserved 4:0 ro 0 reserved. ext_a[8:6] 7:5 rw 0 extended access address [8:6]. this extended access register points to words.
100 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 45. extended memory access (big endian) (ema_be) (34h) table 46. extended memory data high (big endian) (emdh_be) (36h) table 47. extended memory data low (big endian) (emdl_be) (37h) name bit pos. type reset description ext_a[5:1] 4:0 rw 0 extended access address [5:1]. this extended access register points to words. ext_a[0] is hardwired to 0. ext_we[1:0] 6:5 rw 0 extended access write enable. these bits are active-high write enables for word accesses. if both bits are low, a read is performed. if ext_we[1] is high, the contents of ext_d[15:8] is written, and if ext_we[0] is high, the contents of ext_d[7:0] is written. if both bits are high, both data bytes are written. ext_strt_acc 7 rw 0 start access to extended memory. write a 1' to this bit to start the access to the extended memory registers. this bit is automatically cleared when the access is complete. name bit pos. type reset description ext_d[15:8] 7:0 rw 0 extended access data high. the most significant byte of data to be written to extended memory is written here before the extended write begins. the most significant byte of data read from extended memory is available here after the extended read is complete. name bit pos. type reset description ext_d[7:0] 7:0 rw 0 extended access data low. the least significant byte of data to be written to extended memory is written here before the extended write begins. the least significant byte of data read from extended memory is available here after the extended read is complete.
agere systems inc. 101 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2.3 general-purpose i/o control registers table 48. gpio output enable (gpio_oe) (39h) table 49. gpio output value (gpio_ov) (3bh) table 50. gpio input value (gpio_iv) (3dh) name bit pos. type reset description gpio_oe[7:0] 7:0 rw 0 gpio output enable. if this bit is set to 1, the corresponding gpio pin is an output. if cleared to 0, the corresponding gpio pin is an input. name bit pos. type reset description gpio_out[7:0] 7:0 rw 0 gpio output buffer. output bits for the gpio[7:0] pins are written to this buffer. a bit in this buffer is only written to the pin if the corre- sponding output enable bit is high. name bit pos. type reset description gpio_in[7:0] 7:0 ro 0 gpio input buffer. this buffer contains the values at the gpio[7:0] pins.
102 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2.4 control cells table 51. control cell receive direct memory (ccrxdm) (5ch to 93h) the control cell receive memory may also be accessed from extended memory. see table 174. table 52. control cell transmit direct memory (cctxdm) (a0h to d7h) the control cell transmit memory may also be accessed from extended memory. see table 175. name offset type reset description cell_bus_routing_header[15:8] 00h ro x these 56 bytes are the control cell received from the cell bus. this memory space in direct memory is a shadow of the control cell receive extended memory. when present, the control cell should be read from this direct memory space. cell_bus_routing_header[7:0] 01h tandem_routing_header[15:8] 02h tandem_routing_header[7:0] 03h header[31:24] 04h header[23:16] 05h header[15:8] 06h header[7:0] 07h payload_byte0 08h payload_byte1 09h . . . . . . payload_byte46 36h payload_byte47 37h name offset type reset description cell_bus_routing_header[15:8] 00h rw x these 56 bytes are the cell routing header, the tandem routing header, and the control cell to be transmitted onto the cell bus. this memory space in direct memory is a shadow of the control cell transmit extended mem- ory. a control cell to be transmitted should be written to this direct memory space. cell_bus_routing_header[7:0] 01h tandem_routing_header[15:8] 02h tandem_routing_header[7:0] 03h header[31:24] 04h header[23:16] 05h header[15:8] 06h header[7:0] 07h payload_byte0 08h payload_byte1 09h . . . . . . payload_byte46 36h payload_byte47 37h
agere systems inc. 103 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.2.5 multicast memories table 53. phy port 0 and control cells multicast direct memory (pp0mdm) (e0h to ffh) the phy port 0 and control cells multicast memory may also be accessed from extended memory (see table 176). 14.3 extended memory registers the celxpres t8208's extended memory registers are mapped into three major blocks: the main registers, the utopia registers, and the sdram registers. 14.3.1 main registers table 54 . main configuration 1 (mcf1) (0100h) name offset type reset description multicast_receive_enable[15:0] 00h rw x this memory space contains 256 active-high enable bits. each bit represents a multicast net number from 0 through 255. if a bit is set, the cor- responding multicast net number data cell is sent to the queue group for phy port 0, or the corre- sponding multicast control cell is sent to the control cell receive direct and extended memory. the least significant bit is multicast net number 0. this memory space in direct memory is a shadow of the phy port 0 and control cells multicast extended memory space. multicast_receive_enable[31:16] 02h multicast_receive_enable[47:32] 04h . . . . . . multicast_receive_enable[159:144] 12h multicast_receive_enable[175:160] 14h multicast_receive_enable[191:176] 16h multicast_receive_enable[207:192] 18h multicast_receive_enable[223:208] 1ah multicast_receive_enable[239:224] 1ch multicast_receive_enable[255:240] 1eh name bit pos. type reset description reserved 4:0 ro 00h reserved. tram_512k 5 rw 0 translation ram 512k bytes. when a single sram of 512k bytes is used (instead of two 256k bytes sram), this bit should be set to 1. when this bit is set, the tram_qnty_sel and tram_size[1:0] bits in this register are ignored. clear this bit to 0 if a single sram of 512k bytes is not used. bypass_lut 6rw0 bypass lut. when this bit is set to 1, it indicates that no lut option is selected for look up. this means that the cells being received on rx utopia are not going to pass through an lut. when this bit is cleared to 0, the t8208 will perform an lut access for cells being received on rx utopia. cbrh_before_trh 7rw0 cell bus routing header before tandem routing header. when the bypass lut option is set in the above bit, then the t8208 is expecting 58 byte cells in 16-bit utopia mode and 57 byte cells in 8-bit utopia mode on rx utopia. when this bit is cleared to 0 , the t8208 expects to see the tandem routing header come before the cell bus routing header on the incoming cells. when this bit is set to 1, the t8208 device expects to see the cell bus routing header before the tandem routing header on the incoming cells.
104 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 54. main configuration 1 (mcf1) (0100h) (continued) name bit pos. type reset description tx_utopia_hi_z 8 rw 0 transmit utopia high impedance. when the device is in atm and shared utopia mode, this bit must be cleared to 0: n for the slave device, the u_txsoc output will always be high impedance while the u_txdata[7:0] and u_txprty outputs go high impedance when not active. n for the master device, the u_txdata[7:0] and u_txprty outputs go high impedance when not active. when the device is in atm and nonshared utopia mode and this bit is cleared to 0, the u_txdata[7:0] and u_txprty outputs go high impedance when not active. when the device is in phy mode and this bit is cleared to 0, the u_txsoc, u_txdata[7:0], and u_txprty outputs go high impedance when not active. if the device acts as one of the multi-phy devices, then this bit must be cleared to 0. when this bit is set to 1, the u_txsoc, u_txdata[7:0], and u_txprty outputs never go high impedance. sdram_bypass 9rw0 sdram bypass. when this bit is 1, the t8208 will not use sdram and will use only internal memory to buffer cell bus data. clear this bit to enable the sdram interface. phyen 10 rw 1 phy enable. when this bit is 1, the utopia bus is configured for atm mode. when 0, the utopia bus is configured for phy mode. tram_qnty_sel 11 rw 0 translation ram quantity select. when two external sram devices are used, this bit should be set. when this bit is cleared, only one external sram will be accessed using tr_cs*[0]. sp_utopia_sel 12 rw 1 special utopia mode select. when this bit is 1, the t8208 will send 53-byte cells on the utopia bus. when it is 0, the 55-byte utopia mode is selected, and the tandem routing header bytes will be appended to the beginning of each cell. tram_size 14:13 rw 0 translation ram size. these bits identify the size of the external sram used for the look-up table ram. 00 = 32k bytes. 01 = 64k bytes. 10 = 128k bytes. 11 = 256k bytes. reserved 15 rw 0 reserved. program to 0.
agere systems inc. 105 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 55. main interrupt status 1 (mis1) (0102h) note: immediately following device setup, write ffffh to this register to clear erroneously set bits. name bit pos. type reset description cb_wc_miss 0 rol 0 cell bus write clock missing. this bit is set when the cell bus write clock is inactive for 32 mclk cycles. an interrupt is generated if the cor- responding enable bit is set. cb_rc_miss 1 rol 0 cell bus read clock missing. this bit is set when the cell bus read clock is inactive for 32 mclk cycles. an interrupt is generated if the cor- responding enable bit is set. cb_fs_miss 2 rol 0 cell bus frame synchronization signal missing. this bit is set when the cell bus frame sync is not asserted every 16 read clock cycles in 16-user mode or every 32 read clock cycles in 32-user mode. it is also set when cell bus write clock is not present because the frame synchronization signal is clocked onto the cell bus by the write clock. an interrupt is generated if the corresponding enable bit is set. bip8_err 3 rol 0 bit interleave parity error. this bit is set when an error is detected in the bip-8 field of the last cell bus frame cycle. an interrupt is generated if the corresponding enable bit is set. ctrl_cell_ack 4 rol 0 control cell acknowledged. this bit is set when a control cell is sent on the cell bus and an acknowledge is received. this bit is not set for broadcast or multicast cells. an interrupt is generated if the correspond- ing enable bit is set. ctrl_cell_nack 5 rol 0 control cell not acknowledged. this bit is set when a control cell is sent on the cell bus and an acknowledge is not received. this bit is not set for broadcast or multicast cells. an interrupt is generated if the cor- responding enable bit is set. cb_grnt_to 6 rol 0 cell bus grant time-out. this bit is set when a cell bus request has not been granted within the time programmed in the cb_req_to bits. an interrupt is generated if the corresponding enable bit is set. ctrl_cell_sent 7 rol 0 control cell sent. this bit is set when a control cell is sent onto the cell bus. an interrupt is generated if the corresponding enable bit is set. ctrl_cell_av 8 rol 0 control cell available. this bit is set when a control cell is waiting to be read by the microprocessor. an interrupt is generated if the corre- sponding enable bit is set. cb_rh_crc_err 9 rol 0 cell bus routing header crc error. this bit is set when an error is detected in the crc field of the cell bus routing header. an interrupt is generated if the corresponding enable bit is set. rx_prty_err 10 rol 0 receive parity error. this bit is set when the odd parity calculated over the data received on the rx utopia port does not match the u_rxprty signal. an interrupt is generated if the corresponding enable bit is set. when a receive parity error occurs, the cell is still counted as received and is translated and routed. soc_err 11 rol 0 start of cell error. this bit is set when an soc framing error is detected on the rx utopia port. an interrupt is generated if the corre- sponding enable bit is set. when a start of cell error occurs, the received cells are dropped. reserved 15:12 ro 0 reserved.
106 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 56. main interrupt enable 1 (mie1) (0104h) name bit pos. type reset description cb_wc_miss_ie 0 rw 0 cell bus write clock missing interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cb_rc_miss_ie 1 rw 0 cell bus read clock missing interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cb_fs_miss_ie 2 rw 0 cell bus frame synchronization signal missing interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the cor- responding status bit is reset. bip8_err_ie 3 rw 0 bit interleave parity error interrupt enable. an interrupt is gener- ated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. ctrl_cell_ack_ie 4 rw 0 control cell acknowledged interrupt enable. an interrupt is gen- erated if this bit and the corresponding status bit are set. the inter- rupt is generated until this bit or the corresponding status bit is reset. ctrl_cell_nack_ie 5 rw 0 control cell not acknowledged interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cb_grnt_to_ie 6 rw 0 cell bus grant time-out interrupt enable. an interrupt is gener- ated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. ctrl_cell_sent_ie 7 rw 0 control cell sent interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset. ctrl_cell_av_ie 8 rw 0 control cell available interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cb_rh_crc_err_ie 9 rw 0 cell bus routing header crc error interrupt enable. an inter- rupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. rx_prty_err_ie 10 rw 0 receive parity error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gen- erated until this bit or the corresponding status bit is reset. soc_err_ie 11 rw 0 start of cell error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gen- erated until this bit or the corresponding status bit is reset. reserved 15:12 ro 0 reserved.
agere systems inc. 107 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 57. tx utopia clock configuration (txuccf) (010ch) name bit pos. type reset description tx_utopia_clk_div 7:0 rw 01h tx utopia clock division. the selected tx utopia clock source is divided by the number programmed in these bits as follows: 00000000 = reserved 00000001 = no division 00000010 = divide by 2 00000011 = divide by 3 . . . 11111111 = divide by 255 these bits are meaningful only when the t8208 generates the tx utopia clock. tx_utopia_clk_src_sel 9:8 rw 0 tx utopia clock source select. the source of the tx utopia clock is selected via these bits as follows: 00 = cell bus write clock 01 = pll vco frequency (twice the mclk) 10 = pclk 11 = mclk these bits are meaningful only when the t8208 generates the tx utopia clock. reserved 10 ro 0 reserved. program to 0. tx_utopia_clk_en 11 rw 0 tx utopia clock enable. if this bit is 1, the t8208 gener- ates the tx utopia clock on the u_txclk pin. if this bit is 0, the u_txclk pin is configured as an input. reserved 15:12 ro 0 reserved.
108 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 58. rx utopia clock configuration (rxuccf) (010eh) name bit pos. type reset description rx_utopia_clk_div 7:0 rw 01h rx utopia clock division. the selected rx utopia clock source is divided by the number programmed in these bits as follows: 00000000 = reserved 00000001 = no division 00000010 = divide by 2 00000011 = divide by 3 . . . 11111111 = divide by 255 these bits are meaningful only when the t8208 generates the rx utopia clock. rx_utopia_clk_src_sel 9:8 rw 0 rx utopia clock source select. the source of the rx uto- pia clock is selected via these bits as follows: 00 = cell bus write clock 01 = pll vco frequency (twice the mclk) 10 = pclk 11 = mclk these bits are meaningful only when the t8208 ge nerates the rx utopia clock. reserved 10 ro 0 reserved. program to 0. rx_utopia_clk_en 11 rw 0 rx utopia clock enable. if this bit is 1, the t8208 gener- ates the rx utopia clock on the u_rxclk pin. if this bit is 0, the u_rxclk pin is configured as an input . reserved 15:12 ro 0 reserved.
agere systems inc. 109 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 59. main configuration/control (mcfct) (0110h) name bit pos. type reset description cntl_cell_rd 0 wo 0 control cell has been read. w rite 1 to this bit after a control cell is read from the control cell fifo. the 1 will pulse for one clock cycle and will clear to 0 automatically. cntl_cell_wr 1 rw 0 control cell written in control cell memory. write 1 to this bit after a control cell is written in the control cell memory. this bit is automatically cleared when the cell is transmitted to the cell bus. cb_req_pr 3:2 rw 0 cell bus request priority. these bits indicate the priority of stan- dard requests sent on the cell bus as follows: 00 = disabled, receives cells from cell bus but cannot transmit 01 = low priority 10 = medium priority 11 = high priority clp_fill_limit 11:4 rw 0 clp fill limit. these bits indicate the tx phy fifo fill level at which cells with their clp bit set to 1 will be discarded. cell_drop_en 12 rw 0 cell drop enable. if this bit is 1, incoming cells with their clp bit set to 1 will be discarded when the tx phy fifo fill limit pro- grammed in the clp_fill_limit bits is reached. inv_crc 13 rw 0 invert crc. if this bit is 1, the crc-4 in the routing header is inverted before transmission to the cell bus. this bit is used to sim- ulate errors. cb_rx_en 14 rw 1 cell bus receive enable. if this bit is 1, cells are received from the cell bus. if 0, cells are not accepted. slave_en 15 ro 0 slave enable. if this bit is 1, the t8208 is configured as a slave in shared utopia mode. the default value of this bit is 1. clear this bit if shared utopia is not used. for shared utopia, only one of the two devices may have this bit cleared. dynamically changing this bit will cause cell loss. when this bit is 1, u_rxenb*[0] and u_rxenb*[3:1] become inputs.
110 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 60. main configuration 2 (mcf2) (0112h) name bit pos. type reset description addr_clav_en 3:0 rw 0 utopia address, cell available, and enable signals. these bits configure the number of address, cell available, and enable signals on the utopia bus as follows (please see section 9.6 for the phy address selection in 8-bit and 16-bit utopia modes): 0000 = 0 addr, 4 clav; 4enb (8-bit and 16-bit utopia) 0010 = 1 addr, 4 clav; 4enb (8-bit and 16-bit utopia) 0011 = 4 addr, 2 clav; 2enb (8-bit utopia) 0101 = 2 addr, 4 clav; 4enb (8-bit and 16-bit utopia) 1000 = 4 addr, 4 clav; 4enb (8-bit utopia) 1001 = 3 addr, 4 clav; 4enb. (16-bit utopia) 1011 = 3 addr, 4 clav; 4enb (8-bit utopia) other modes are reserved. reserved 4 ro 0 reserved. program to 0. dont_inhibit_rxphy_clav 5 rw 0 dont inhibit rx phy_clav. this bit, when set to 1, keeps the rx_clav signal always asserted high, indicating the capability to accept cells even if the rx utopia fifo could overrun, or is actually overrun. this bit is valid only when the rx utopia is in phy mode. when this bit is cleared to 0 , the rx_clav signal is deas- serted if the rx utopia fifo is considered full. inhibit_rxuto_fifo_overrun 6 rw 0 inhibit rx utopia fifo overrun. this bit, when set to 1, prevents the rx utopia fifo from overflowing by deas- serting its rx_enb* signal, even though the rx_clav signal is high when polled, if the rx utopia fifo is considered full. it is considered full when 4 cells are stored in it that have not yet been read and processed by the t8208. this bit is valid when the rx utopia is in atm mode. when this bit is cleared to 0 , the rx_enb* signal is not deas- serted even if the rx utopia fifo is considered full. utopia_16bit 7 rw 0 utopia 16-bit. when this bit is set to 1, the tx and rx utopia interfaces are 16 bits wide (instead of 8 bits). this mode achieves the oc-12 rate on the utopia interfaces. when this bit is cleared to 0 , the tx and rx utopia inter- faces are 8 bits wide.
agere systems inc. 111 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 60. main configuration 2 (mcf2) (0112h) (continued) name bit pos. type reset description div_queue 10:8 rw 0 divide into queues. these bits indicate the number of queues used in the tx utopia cell buffer as follows: 000 = 4 queues64 cells per queue 001 = 8 queues32 cells per queue 010 = 16 queues16 cells per queue 011 = 32 queues8 cells per queue 100 = 64 queues4 cells per queue 101 = 128 queues2 cells per queue 111 = 1 queue256 cells per queue in phy mode, the maximum number of queues that can be selected are four. to maximize cell buffering the number of queues must be one. in multi-phy mode, each phy port uses four queues unless 64 phy ports are selected (in 8-bit utopia mode). if 64 phy ports are selected, each phy port uses two queues or a programmable number of queues per phy. in 16-bit utopia mode, each phy port uses four queues, unless 32 phy ports are selected. if 32 phy ports are selected, each phy port uses two queues or a programmable number of queues per phy. reserved 11 ro 0 reserved. program to 0. clear_on_read 12 rw 1 clear on read. when this bit is set to 1 , the following counters are going to be automatically cleared when read by the microprocessor: n rx phy cell counters (incoming cell count) 4000h 40feh. n tx phy cell counters (outgoing cell count) 0600h06feh. n dropped cell counters 3000h31feh. n total and special cell counters of the look-up record if the extended records mode is selected. both the registers for every phy (and every queue for dropped cell count) must be read consecutively (bits 31:16 first, bits 15:0 next). when this bit is cleared to 0 , the microprocessor must clear the counters after it reads them, if it is needed. mask_ignore 13 rw 0 mask ignore. when this bit is set to 1, the t8208 ignores the ignore bit that was programmed in the look-up records that control the transla- tion of the incoming utopia cells. when this bit is cleared to 0 , the t8208 processes the ignore bit pro- grammed in the look-up records.
112 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 60. main configuration 2 (mcf2) (0112h) (continued) name bit pos. type reset description initialize_counters 14 rw 0 initialize counters. this bit can be set and polled until it goes back to zero to indicate the completion of clearing the following counters during the initialization process: n rx phy cell counters (incoming cell count) 4000h 40feh. n tx phy cell counters (outgoing cell count) 0600h06feh. n dropped cell counters 3000h31feh. note that this bit does not clear the total and special cell counters of the look-up record if the extended records mode is selected. the user could set this bit to 1, initialize other regis- ters if desired, and at the end come back to poll this bit before removing the reset from the main circuitry. note that this feature will not work unless the main registers are out of reset and the remaining circuitry is in reset. (this bit can be used to clear the above counters as part of the extended memory access after the srst_reg* is set as part of the powerup sequence; see section 3 on page 22). initialize_lut 15 rw 0 initialize lut. this bit can be set and polled until it goes back to zero to indicate the completion of clearing the look-up table. note that the memory size in the sram indicated by the bits set in 0100h will be cleared, not the maximum possible size of the sram, unless the configuration bits of register 0100h indicate that the largest possible sram size is being used. the user could set this bit to 1, initialize other registers if desired, and, at the end, come back to poll this bit before remov- ing the reset from the main circuitry. note that this feature will not work unless the main registers are out of reset and the remaining circuitry is in reset. (this bit can be used to clear the above counters as part of the extended memory access after the srst_reg* is set as part of the powerup sequence; see section 3 on page 22).
agere systems inc. 113 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 61. utopia configuration (ucf) (0114h) table 62. main configuration 3 (mcf3) (0116h) name bit pos. type reset description hec_mask 7:0 rw 55h header error control (hec) mask. an exclusive-or function is performed on these bits and the hec value received from the utopia bus before the hec is checked for error. also, an exclu- sive-or function is performed on these bits and the hec value calculated before it is transmitted on the utopia bus. note that a value of zero will not change the hec value, and a value of ffh will invert the hec value. addr_match 12:8 rw 0 address match. these bits represent the utopia address of the t8208 in level 2 utopia multi-phy mode. these bits are only used when the t8208 is configured as a phy. reserved 15:13 ro 0 reserved. name bit pos. type reset description cb_req_to 7:0 rw 0 cell bus request time-out. these bits determine the number of frames that a cell bus request may be present before the cell bus grant time-out (cb_grnt_to) status bit is set. gfc_value 11:8 rw 0 generic flow control (gfc) value. these are the bits inserted in the gfc field of the tx utopia outgoing cells when the gfc insert feature is enabled. gfc_insert_en 12 rw 0 gfc insert enable. if this bit is 1, the gfc_value will be inserted in all cells transmitted to the utopia bus. reserved 15:13 ro 0 reserved.
114 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 63. utopia configuration 5 (ucf5) (0118h) table 64. utopia configuration 4 (ucf4) (011ah) table 65. utopia configuration 3 (ucf3) (011ch) table 66. utopia configuration 2 (ucf2) (011eh) name bit pos. type reset description rx_port_en[63:48] 15:0 rw 0 receive port enable. each bit in this field represents one of the 48 63 phy ports where the least significant bit is port 48. if the corresponding bit is 1, cells will be received on the designated utopia port. name bit pos. type reset description rx_port_en[47:32] 15:0 rw 0 receive port enable. each bit in this field represents one of the 32 47 phy ports where the least significant bit is port 32. if the corresponding bit is 1, cells will be received on the designated utopia port. name bit pos. type reset description rx_port_en[31:16] 15:0 rw 0 receive port enable. each bit in this field represents one of the 16 31 phy ports where the least significant bit is port 16. if the corresponding bit is 1, cells will be received on the designated utopia port. name bit pos. type reset description rx_port_en[15:0] 15:0 rw 0 receive port enable. each bit in this field represents one of the 0 15 phy ports where the least significant bit is port 0. if the cor- responding bit is 1, cells will be received on the designated uto- pia port.
agere systems inc. 115 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) refer to section 8.4 for descriptions of special cell counters. table 67. extended lut control (elutcn) (0120h) name bit pos. type reset description spc_cell_cnt_sel0 0 rw 0 special cell count select 0. when this bit is 1, cells, whose four least significant bits of their header are 0000, are counted in the special cell count. spc_cell_cnt_sel1 1 rw 0 special cell count select 1. when this bit is 1, cells, whose four least significant bits of their header are 0001, are counted in the special cell count. spc_cell_cnt_sel2 2 rw 0 special cell count select 2. when this bit is 1, cells, whose four least significant bits of their header are 0 010, are counted in the special cell count. spc_cell_cnt_sel3 3 rw 0 special cell count select 3. when this bit is 1, cells, whose four least significant bits of their header are 0 011, are counted in the special cell count. spc_cell_cnt_sel4 4 rw 0 special cell count select 4. when this bit is 1, cells, whose four least significant bits of their header are 0 100, are counted in the special cell count. spc_cell_cnt_sel5 5 rw 0 special cell count select 5. when this bit is 1, cells, whose four least significant bits of their header are 0 101, are counted in the special cell count. spc_cell_cnt_sel6 6 rw 0 special cell count select 6. when this bit is 1, cells, whose four least significant bits of their header are 0 110, are counted in the special cell count. spc_cell_cnt_sel7 7 rw 0 special cell count select 7. when this bit is 1, cells, whose four least significant bits of their header are 0 111, are counted in the special cell count. spc_cell_cnt_sel8 8 rw 0 special cell count select 8. when this bit is 1, cells, whose four least significant bits of their header are 1000, are counted in the special cell count. spc_cell_cnt_sel9 9 rw 0 special cell count select 9. when this bit is 1, cells, whose four least significant bits of their header are 1001, are counted in the special cell count. spc_cell_cnt_sel10 10 rw 0 special cell count select 10. when this bit is 1, cells, whose four least significant bits of their header are 1010, are counted in the spe- cial cell count. spc_cell_cnt_sel11 11 rw 0 special cell count select 11. when this bit is 1, cells, whose four least significant bits of their header are 1011, are counted in the spe- cial cell count. spc_cell_cnt_sel12 12 rw 0 special cell count select 12. when this bit is 1, cells, whose four least significant bits of their header are 1100, are counted in the spe- cial cell count. spc_cell_cnt_sel13 13 rw 0 special cell count select 13. when this bit is 1, cells, whose four least significant bits of their header are 1101, are counted in the spe- cial cell count. spc_cell_cnt_sel14 14 rw 0 special cell count select 14. when this bit is 1, cells, whose four least significant bits of their header are 1110, are counted in the special cell count. spc_cell_cnt_sel15 15 rw 0 special cell count select 15. when this bit is 1, cells, whose four least significant bits of their header are 1111, are counted in the special cell count.
116 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 68. generated cell bus clocks control register (gcbccr) (0122h) the cb_gen_wc and cb_gen_rc clocks are ttl compatible and hence the customer needs to use an external gtl+ driver. name bit pos. type reset description divisor_value 7:0 rw 00000010 divisor value. these bits contain the divisor value that is used to divide one of the three clock sources down to gener- ate the cb_gen_wc and cb_gen_rc clocks that are available on pins a3 and b4 of the t8208. the divisor controls both clocks, as cb_gen_wc is obtained by simply delaying cb_gen_rc by a certain programmable value. 00000000 = reserved 00000001 = no division 00000010 = divide by 2 00000011 = divide by 3 . . . 11111111 = divide by 255 clock_select 9:8 rw 10 clock select. these bits select one of the following clocks as the source of the i/o clocks, cb_gen_wc and cb_gen_rc: "00: reserved. "01: pll vco frequency (twice the mclk). "10: pclk "11: mclk. clock_enable 10 rw 0 clock enable. when this bit is set to 1, the generated cell bus clocks come out on the cb_gen_wc and cb_gen_rc pins (a3 and b4 respectively) and also drive the internal cell bus logic of this generating device if select_gtl_clocks (bit 6) in register 2eh is cleared to 0. when this bit is cleared to 0, the cb_gen_wc and cb_gen_rc pins are 3-stated and are inactive. note: due to the inherent propagation delay between the clocks that drive the cell bus logic of the generating device and the other devices on the backplane, it is recommended that customers set bit 6 in register 2eh to 1 and set bit 10 in register 0122h to 1 and route these generated clocks (through a gtl+ driver) back to the cb_wc* and cb_rc* pins (pins a10 and b10, respectively). switching_complete 11 rw 0 switching complete. when this bit is set by the t8208 inter- nal logic to 1, it indicates that the new clock source that was programmed in bits 9:8 has now taken over as the source of cb_gen_wc and cb_gen_rc. there is no need to clear this bit as it is automatically cleared when a new source is selected.
agere systems inc. 117 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 68. generated cell bus clocks control register (gcbccr) (0122h) (continued) the cb_gen_wc and cb_gen_rc clocks are ttl compatible and hence the customer needs to use an external gtl+ driver. note: the following should be done when attempting to source the generated clocks from a new source: a. program the new clock_select value into register 122 hex. b. poll bit 11 of register 122 hex until it is set to 1'. note: the following should be done when attempting to program a new divisor for the generated clocks: a. program the new divisor_value into register 122 hex. b. poll bit 12 of register 122 hex until it is set to 1'. note: the following should be done when attempting to do a handoff of the generated clocks on the backplane from one device to another: a. set the clock_enable bit of register 122 hex in the presently generating t8208 to 0'. b. poll bits 0 and 1 of register 102 hex (cb_wc_miss and cb_rc_miss) until they both become high, indi- cating that the cell bus clocks were found to be dead for 32 consecutive mclk cycles. c. if needed, program the new clock source into register 122 hex of the new t8208 clock master as per the procedure outlined above. d. if needed, program the new divisor value into register 122 hex of the new t8208 clock master as per the procedure outlined above. e. enable the new generated clocks from the new t8208 by setting the clock_enable bit of register 122 hex. f. read bits 2:0 of register 102 hex (cb_fs_miss, cb_rc_miss and cb_wc_miss). g. if the bits read in step f (above) are set to 1, proceed to step h; else, go to step i. h. clear those 3 bits by writing a 1 to them (in register 102 hex). go back to step f. i. handoff is done. note: the above delay_select bits have an accuracy of +10% and C50%. name bit pos. type reset description divisor_active 12 rw 0 divisor active. when this bit is set by the t8208 internal logic to 1, it indicates that the new divisor value that was just programmed in bits 7:0 of this register is now in effect in divid- ing the cb_gen_wc and cb_gen_rc. there is no need to clear this bit as it is automatically cleared when a new divisor is selected. delay_select 15:13 rw 010 delay select. these bits control the delay to be observed between cb_gen_wc and cb_gen_rc. the range of program- mable delays are: "000: 1.0 ns. "001: 1.5 ns. "010: 2.0 ns. "011: 2.5 ns. "100: 3.0 ns. "101: 3.5 ns. "110: 4.0 ns. "111: 4.5 ns.
118 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 69. rx phy fifo thresholds to change cell bus request priority (rxpftcrp) (0126h) note: when bits 3:2 in register 0110h are set to 00 (disabled) and this feature is enabled, cells are transmitted onto the cell bus as soon as the priority medium is reached. to prevent this, either the feature needs to be disabled or cells should not be transmitted to this fifo. note: these threshold levels cannot be changed when there is data flowing through the celxpres device. name bit pos. type reset description cb_prio2_thr 3:0 rw 1111 cell bus priority 2 threshold. these bits contain the rx phy fifo threshold level value after which the cell bus request priority will be set to high in an attempt to flush the cells from the rx phy fifo onto the backplane. cb_prio2_thr_en 4 rw 0 cell bus priority 2 threshold enable. when this bit is set to 1, it enables the change in the cell bus request pri- ority to its highest value (as mentioned in bits 3:0 above). reserved 7:5 ro 000 reserved. cb_prio1_thr 11:8 rw 1111 cell bus priority 1 threshold. these bits contain the rx phy fifo threshold level value after which the cell bus request priority will be set to medium in an attempt to flush the cells from the rx phy fifo onto the backplane. cb_prio1_thr_en 12 rw 0 cell bus priority 1 threshold enable. when this bit is set to 1, it enables the change in the cell bus request pri- ority to its medium value (as mentioned in bits 11:8 above). reserved 15:13 ro 000 reserved. the information below shows the change in cell bus request priority when cell bus priority 1 threshold and cell bus priority 2 threshold are reached. cell bus request priority bits 3:2 in register 0110h priority when threshold 1 is reached priority when threshold 2 is reached 00 = disabled medium high 01 = low priority medium high 10 = medium priority medium high 11 = high priority high high
agere systems inc. 119 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 70. enable request on upper backplane address (erub) (012ch) table 71. enable request on lower backplane address (erlb) (012eh) name bit pos. type reset description en_req_ up_bp 15:0 rw ffffh enable request on upper backplane. when set to one, the arbiter t8208, in which this register is programmed, will recognize and process the requests on the backplane with device addresses in the range 16 31. bit 0 corresponds to device address 16, bit 1 to device address 17, etc. when any bit is cleared to 0, the device address associated with that bit will not have its request served on the backplane. it is strongly recommended that, in the case that a customer has a master card that acts as the arbiter, and a slave card that acts as a backup and is switched as the arbiter in the event that the master card fails, the same value be programmed in this register for both the master and the slave cards. name bit pos. type reset description en_req_ low_bp 15:0 rw ffffh enable request on lower backplane. when set to one, the arbiter t8208, in which this register is programmed, will recognize and process the requests on the backplane with device addresses in the range 0 15. bit 0 corresponds to device address 0, bit 1 to device address 1, etc. when any bit is cleared to 0, the device address associated with that bit will not have its request served on the backplane. it is strongly recommended that, in the case that a customer has a master card that acts as the arbiter, and a slave card that acts as a backup and is switched as the arbiter in the event that the master card fails, the same value be programmed in this register for both the master and the slave cards.
120 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 72. cell bus configuration/status (cbcfs) (0130h) name bit pos. type reset description unit_addr* 4:0 rw ua*[4:0] unit address. these bits indicate the values at the pins ua*[4:0] (backplane device address). these bits are read-only if bit 7 in this register is cleared to 0 and writable if bit 7 is set to 1 . when these bits are written to, the value written over- writes the address on the pins ua*[4:0] and this new value will be the backplane address of the t8208. cb_arb_sel* 5 rw 1 cell bus arbiter select. if this bit is 0, cell bus arbiter is selected. only one device on the cell bus may be configured as arbiter. all other devices should set this bit to 1. cb_usr_mode 6 rw 0 cell bus user mode. if this bit is 0, 32-user mode is selected on the cell bus. if 1, 16-user mode is selected. use_prog_addr 7 rw 0 use programmed address. when this bit is set to 1, it allows the microprocessor to program any address (that can be different from the address on pins ua*[4:0]) in bits [4:0] of this register and ignores the address programmed at pins ua*[4:0]. set this bit to 1 and then program the new address into bits 4:0. insert_cb_lpbk_hdr 8 rw 1 insert cell bus loopback header. when this bit is set to 1, the t8208 inserts the programmed loopback header (in regis- ter address 0136h) as the new cell bus routing header of the loopback cell. if this bit is cleared to 0, the t8208 uses the tandem routing header of the incoming loopback cell as the new cell bus routing header of the outgoing loopback cell, and as a result, also inserts the programmed loopback header (in register address 0136h) as the tandem routing header of the outgoing loopback cell. cntrl_cell_prio 9 rw 0 control cell priority. if this bit is cleared to 0, then cells from the rx phy fifo have the highest priority, cells from the con- trol cell tx fifo have next highest, and finally, cells from the loopback fifo have the lowest. if this bit is set to 1, then cells from the control cell tx fifo have the highest priority, cells from the rx phy fifo have the next highest priority, and finally cells from the loopback fifo have the lowest priority. note: it is recommended that this bit be set during the pow- erup/reset sequence (section 3), if necessary. it is strongly advised not to set this bit during data flow. reserved 15:10 ro 0 reserved.
agere systems inc. 121 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 73. main interrupt status 2 (mis2) (0132h) name bit pos. type reset description lb_cell_lost 0 rol 0 loopback cell lost. this bit is set if a loopback cell is discarded when the loopback fifo is full. an interrupt is generated if the corresponding enable bit is set. reserved 1 rol 0 reserved. cb_in_fifo_ovrn 2 rol 0 cell bus input fifo overrun. this bit is set if the four- cell incoming cell bus input fifo overflows. if this bit becomes set, mclk may be too slow compared to the cb_wc* input. an interrupt is generated if the correspond- ing enable bit is set. tx_phy_fifo_ovrn 3 rol 0 tx phy fifo overrun. this bit is set if the 256-cell tx phy fifo overflows. if this bit becomes set, bandwidth to the sdram may be insufficient. an interrupt is generated if the corresponding enable bit is set. cell_clp1_dis 4 rol 0 cell with clp set to one discarded. this bit is set if a cell with its clp bit set to one is discarded when the 256- cell tx phy fifo goes over the clp_fill_limit. an interrupt is generated if the corresponding enable bit is set. rx_utopia_fifo_ovrn 5 rol 0 rx utopia fifo overrun. this bit is set if the rx uto- pia fifo overflows. if this bit becomes set, bandwidth to the translation ram or the cell bus may be insufficient. an interrupt is generated if the corresponding enable bit is set. cntl_cell_rx_fifo_ovrn 6 rol 0 control cell rx fifo overrun. this bit is set when the control cell rx fifo overflows. an interrupt is generated if the corresponding enable bit is set. reserved 15:7 ro 0 reserved.
122 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 74. main interrupt enable 2 (mie2) (0134h) table 75 . loopback (lb) (0136h) table 76 . extended lut configuration (elutcf) (0138h) name bit pos. type reset description lb_cell_lost_ie 0 rw 0 loopback cell lost interrupt enable. an interrupt is gener- ated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. reserved 1 rw 0 reserved. program this bit to zero. cb_in_fifo_ovrn_ie 2 rw 0 cell bus input fifo overrun interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. tx_phy_fifo_ovrn_ie 3 rw 0 tx phy fifo overrun interrupt enable. an interrupt is gen- erated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cell_clp1_dis_ie 4 rw 0 cell with clp set to one discarded interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corre- sponding status bit is reset. rx_utopia_fifo_ovrn_ie 5 rw 0 rx utopia fifo overrun interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. cntl_cell_rx_fifo_ovrn_ie 6 rw 0 control cell rx fifo overrun interrupt enable. an inter- rupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corre- sponding status bit is reset. reserved 15:7 ro 0 reserved. name bit pos. type reset description loopback_cbrh 15:0 rw 0 loopback cell bus routing header. bits 15:4 of this register will act as the new cell bus routing header of the outgoing loopback cell, if bit 8 of register 0130h is set to 1 . if bit 8 of register 0130h is cleared to 0, the contents (bits 15:0) of this register will be used as the tandem rout- ing header of the outgoing loopback cell. if the contents of this register are used as the cell bus routing header, then the crc4 need not be calculated, as the t8208 automatically cal- culates it and prepends it (in bits 3:0 of this register) for all outgoing cells. name bit pos. type reset description lut_rec_form 1:0 rw 0 lut record format. these bits indicate the format of the lut records as follows: "00: 8 byte records. "01: 16 byte record with extended monitoring. "10. reserved. "11: reserved.
agere systems inc. 123 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 77 . misrouted cell lut 3 (mlut3) (013ch) table 78 . misrouted cell lut 2 (mlut2) (013eh) table 79 . misrouted cell lut 1 (mlut1) (0140h) table 80 . misrouted cell lut 0 (mlut0) (0142h) name bit pos. type reset description mis_cell_lut_sel[63:48] 15:0 rw ffffh misrouted cell lut select. each bit in this field repre- sents one of the 48 63 phy ports. the least significant bit is phy port 48. if the corresponding bit is 1, misrouted cells from a phy port are monitored. name bit pos. type reset description mis_cell_lut_sel[47:32] 15:0 rw ffffh misrouted cell lut select. each bit in this field repre- sents one of the 3247 phy ports. the least significant bit is phy port 32. if the corresponding bit is 1, misrouted cells from a phy port are monitored. name bit pos. type reset description mis_cell_lut_sel[31:16] 15:0 rw ffffh misrouted cell lut select. each bit in this field repre- sents one of the 1631 phy ports. the least significant bit is phy port 16. if the corresponding bit is 1, misrouted cells from a phy port are monitored. name bit pos. type reset description mis_cell_lut_sel[15:0] 15:0 rw ffffh misrouted cell lut select. each bit in this field repre- sents one of the 015 phy ports. the least significant bit is phy port 0. if the corresponding bit is 1, misrouted cells from a phy port are monitored.
124 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 81. misrouted cell lut 4 (mlut4) (0144h) table 82. misrouted cell header high (mchh) (0146h) table 83. misrouted cell header low (mchl) (0148h) name bit pos. type reset description mis_cell_clr 0 wo 0 misrouted cell header clear. write 1 to this bit to clear the previously latched misrouted cell header. the 1 will pulse for one clock cycle and will clear to 0 automatically. mis_cell_latch 1 ro 0 misrouted cell header latched. if this bit is set to 1, a misrouted cell was detected and is stored to the mis_cell_header bits. reserved 3:2 ro 0 reserved. lst_mis_cell_lut 9:4 ro 0 last misrouted cell lut. these bits indicate the phy port from which the last misrouted cell was latched. reserved 15:10 ro 0 reserved. name bit pos. type reset description mis_cell_header[31:16] 15:0 ro 0 misrouted cell header bits [31:16]. these bits are cell header bits [31:16] from the first misrouted cell received after the mis_cell_clr bit was set. a cell is considered mis- routed if its a and i bits are 00, if its vci is out of range, or if the lutx_vpi_chk bit is 1 and the unused vpi bits in the incoming cell header are not all zero. name bit pos. type reset description mis_cell_header[15:0] 15:0 ro 0 misrouted cell header bits [15:0]. these bits are cell header bits [15:0] from the first misrouted cell received after the mis_cell_clr bit was set. a cell is considered mis- routed if its a and i bits are 00, if its vci is out of range, or if the lutx_vpi_chk bit is 1 and the unused vpi bits in the incoming cell header are not all zero.
agere systems inc. 125 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.2 utopia registers table 84. hec interrupt status 3 (his3) (0300h) table 85. hec interrupt status 2 (his2) (0302h) table 86. hec interrupt status 1 (his1) (0304h) table 87. hec interrupt status 0 (his0) (0306h) name bit pos. type reset description hec_err [63:48] 15:0 rol 0 hec error. each bit in this field represents one of the 48 63 phy ports where the least significant bit is port 48. the associ- ated bit is set when an hec error is detected on the phy port. an interrupt is generated if the corresponding enable bit is set. when a hec error occurs, the cell is still counted as received and is translated and routed. name bit pos. type reset description hec_err [47:32] 15:0 rol 0 hec error. each bit in this field represents one of the 3247 phy ports where the least significant bit is port 32. the associ- ated bit is set when an hec error is detected on the phy port. an interrupt is generated if the corresponding enable bit is set. when a hec error occurs, the cell is still counted as received and is translated and routed. name bit pos. type reset description hec_err [31:16] 15:0 rol 0 hec error. each bit in this field represents one of the 1631 phy ports where the least significant bit is port 16. the associ- ated bit is set when an hec error is detected on the phy port. an interrupt is generated if the corresponding enable bit is set. when a hec error occurs, the cell is still counted as received and is translated and routed. name bit pos. type reset description hec_err [15:0] 15:0 rol 0 hec error. each bit in this field represents one of the 015 phy ports where the least significant bit is port 0. the associ- ated bit is set when an hec error is detected on the phy port. an interrupt is generated if the corresponding enable bit is set. when a hec error occurs, the cell is still counted as received and is translated and routed.
126 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 88. hec interrupt enable 3 (hie3) (0308h) table 89. hec interrupt enable 2 (hie2) (030ah) table 90. hec interrupt enable 1 (hie1) (030ch) table 91. hec interrupt enable 0 (hie0) (030eh) name bit pos. type reset description hec_err_ie [63:48] 15:0 rw 0 hec error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset. name bit pos. type reset description hec_err_ie [47:32] 15:0 rw 0 hec error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset. name bit pos. type reset description hec_err_ie [31:16] 15:0 rw 0 hec error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset. name bit pos. type reset description hec_err_ie [15:0] 15:0 rw 0 hec error interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset.
agere systems inc. 127 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 92 . lut interrupt service request 3 (lutisr3) (0310h) table 93 . lut interrupt service request 2 (lutisr2) (0312h) table 94 . lut interrupt service request 1 (lutisr1) (0314h) table 95 . lut interrupt service request 0 (lutisr0) (0316h) name bit pos. type reset description lut_int_serv[63:48] 15:0 ro 0 lut interrupt service. each bit in this field represents one of the 48 63 lut configuration/status registers. the least sig- nificant bit represents lut 48 configuration/status register. if the corresponding bit is 1, the specific lut configuration/sta- tus register has interrupt status bits that need servicing. name bit pos. type reset description lut_int_serv[47:32] 15:0 ro 0 lut interrupt service. each bit in this field represents one of the 32 47 lut configuration/status registers. the least sig- nificant bit represents lut 32 configuration/status register. if the corresponding bit is 1, the specific lut configuration/sta- tus register has interrupt status bits that need servicing. name bit pos. type reset description lut_int_serv[31:16] 15:0 ro 0 lut interrupt service. each bit in this field represents one of the 16 31 lut configuration/status registers. the least sig- nificant bit represents lut 16 configuration/status register. if the corresponding bit is 1, the specific lut configuration/sta- tus register has interrupt status bits that need servicing. name bit pos. type reset description lut_int_serv[15:0] 15:0 ro 0 lut interrupt service. each bit in this field represents one of the 0 15 lut configuration/status registers. the least signif- icant bit represents lut 0 configuration/status register. if the corresponding bit is 1, the specific lut configuration/status register has interrupt status bits that need servicing.
128 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 96. lut x configuration/status (lutxcfs) (0320h to 039eh) name bit pos. type reset description lut_en 0 rw 0 lut memory space enable. if this bit is 1, the lut memory space is enabled. when this bit is 0, cells from the associated phy port are discarded, are not flagged as misrouted, and are not counted as a received cell. reserved 3:1 ro 0 reserved. mis_cell 4 rol 0 misrouted cell to lut. this bit is set when a cells translation record has its a and i bits equal to 0. an interrupt is gener- ated if the corresponding enable bit is set. vci_or 5 rol 0 vci out of range. this bit is set when an incoming cells vci is greater than the allowed range. an interrupt is generated if the corresponding enable bit is set. vpi_or 6 rol 0 vpi out of range. this bit is set when one of the incoming cells unmasked vpi bits is not 0 and the lutx_vpi_chk bit equals 1. an interrupt is generated if the corresponding enable bit is set. reserved 9:7 ro 0 reserved. mis_cell_ie 10 rw 0 misrouted cell to lut interrupt enable. an interrupt is gen- erated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. vci_or_ie 11 rw 0 vci out of range interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. vpi_or_ie 12 rw 0 vpi out of range interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. reserved 15:13 ro 0 reserved. the letter x in the register name represents the 64 phy port look-up tables. the addresses of the 64 configura- tion/status registers are shown below. register name register address register name register address lut 0 configuration/status (0320h) lut 13 configuration/status (033ah) lut 1 configuration/status (0322h) lut 14 configuration/status (033ch) lut 2 configuration/status (0324h) lut 15 configuration/status (033eh) lut 3 configuration/status (0326h) lut 16 configuration/status (0340h) lut 4 configuration/status (0328h) lut 17 configuration/status (0342h) lut 5 configuration/status (032ah) lut 18 configuration/status (0344h) lut 6 configuration/status (032ch) lut 19 configuration/status (0346h) lut 7 configuration/status (032eh) lut 20 configuration/status (0348h) lut 8 configuration/status (0330h) lut 21 configuration/status (034ah) lut 9 configuration/status (0332h) lut 22 configuration/status (034ch) lut 10 configuration/status (0334h) lut 23 configuration/status (034eh) lut 11 configuration/status (0336h) lut 24 configuration/status (0350h) lut 12 configuration/status (0338h) lut 25 configuration/status (0352h)
agere systems inc. 129 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 96. lut x configuration/status (lutxcfs) (0320h to 039eh) (continued) register name register address register name register address lut 26 configuration/status (0354h) lut 45 configuration/status (037ah) lut 27 configuration/status (0356h) lut 46 configuration/status (037ch) lut 28 configuration/status (0358h) lut 47 configuration/status (037eh) lut 29 configuration/status (035ah) lut 48 configuration/status (0380h) lut 30 configuration/status (035ch) lut 49 configuration/status (0382h) lut 31 configuration/status (035eh) lut 50 configuration/status (0384h) lut 32 configuration/status (0360h) lut 51 configuration/status (0386h) lut 33 configuration/status (0362h) lut 52 configuration/status (0388h) lut 34 configuration/status (0364h) lut 53 configuration/status (038ah) lut 35 configuration/status (0366h) lut 54 configuration/status (038ch) lut 36 configuration/status (0368h) lut 55 configuration/status (038eh) lut 37 configuration/status (036ah) lut 56 configuration/status (0390h) lut 38 configuration/status (036ch) lut 57 configuration/status (0392h) lut 39 configuration/status (036eh) lut 58 configuration/status (0394h) lut 40 configuration/status (0370h) lut 59 configuration/status (0396h) lut 41 configuration/status (0372h) lut 60 configuration/status (0398h) lut 42 configuration/status (0374h) lut 61 configuration/status (039ah) lut 43 configuration/status (0376h) lut 62 configuration/status (039ch) lut 44 configuration/status (0378h) lut 63 configuration/status (039eh)
130 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.2.1 tx utopia configuration table 97. master queue 7 (mq7) (0150h) these bits indicate which queues in the master device are enabled for shared utopia mode. table 98. master queue 6 (mq6) (0152h) these bits indicate which queues in the master device are enabled for shared utopia mode. table 99. master queue 5 (mq5) (0154h) these bits indicate which queues in the master device are enabled for shared utopia mode. name bit pos. type reset description mast_queue_in[127:112] 15:0 rw 0 master queue indication [127:112]. each bit in this field represents one of the 112 127 queues in the master device, where the least significant bit is queue 112, and most significant bit is queue 127. these bits indicate which queues in the master device are enabled for shared uto- pia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode. name bit pos. type reset description mast_queue_in[111:96] 15:0 rw 0 master queue indication [111:96]. each bit in this field rep- resents one of the 96 111 queues in the master device, where the least significant bit is queue 96, and most signifi- cant bit is queue 111. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode. name bit pos. type reset description mast_queue_in[95:80] 15:0 rw 0 master queue indication [95:80]. each bit in this field rep- resents one of the 80 95 queues in the master device, where the least significant bit is queue 80, and most signifi- cant bit is queue 95. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode.
agere systems inc. 131 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 100. master queue 4 (mq4) (0156h) these bits indicate which queues in the master device are enabled for shared utopia mode. table 101. master queue 3 (mq3) (0158h) these bits indicate which queues in the master device are enabled for shared utopia mode. table 102. master queue 2 (mq2) (015ah) these bits indicate which queues in the master device are enabled for shared utopia mode. name bit pos. type reset description mast_queue_in[79:64] 15:0 rw 0 master queue indication [79:64]. each bit in this field rep- resents one of the 64 79 queues in the master device, where the least significant bit is queue 64, and most signifi- cant bit is queue 79. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode. name bit pos. type reset description mast_queue_in[63:48] 15:0 rw 0 master queue indication [63:48]. each bit in this field rep- resents one of the 48 63 queues in the master device, where the least significant bit is queue 48, and most signifi- cant bit is queue 63. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode. name bit pos. type reset description mast_queue_in[47:32] 15:0 rw 0 master queue indication [47:32]. each bit in this field rep- resents one of the 32 47 queues in the master device, where the least significant bit is queue 32, and most signifi- cant bit is queue 47. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode.
132 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 103. master queue 1 (mq1) (015ch) these bits indicate which queues in the master device are enabled for shared utopia mode. table 104. master queue 0 (mq0) (015eh) these bits indicate which queues in the master device are enabled for shared utopia mode. name bit pos. type reset description mast_queue_in[31:16] 15:0 rw 0 master queue indication [31:16]. each bit in this field rep- resents one of the 16 31 queues in the master device, where the least significant bit is queue 16, and most signifi- cant bit is queue 31. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode. name bit pos. type reset description mast_queue_in[15:0] 15:0 rw 0 master queue indication [15:0]. each bit in this field repre- sents one of the 0 15 queues in the master device, where the least significant bit is queue 0, and most significant bit is queue 15. these bits indicate which queues in the master device are enabled for shared utopia mode. if the associ- ated bit is 1, it indicates that the queue is enabled. note: these bits must be programmed even when the device is not used in shared utopia mode.
agere systems inc. 133 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 105. slave queue 7 (sq7) (0160h) table 106. slave queue 6 (sq6) (0162h) name bit pos. type reset description slav_queue_in[127:112] 15:0 rw 0 slave queue indication [127:112]. each bit in this field represents one of the 112 127 queues in the slave device, where the least significant bit is queue 112, and most signif- icant bit is queue 127. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device. name bit pos. type reset description slav_queue_in[111:96] 15:0 rw 0 slave queue indication [111:96]. each bit in this field rep- resents one of the 96 111 queues in the slave device, where the least significant bit is queue 96, and most signifi- cant bit is queue 111. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device.
134 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 107. slave queue 5 (sq5) (0164h) table 108. slave queue 4 (sq4) (0166h) table 109. slave queue 3 (sq3) (0168h) name bit pos. type reset description slav_queue_in[95:80] 15:0 rw 0 slave queue indication [95:80]. each bit in this field rep- resents one of the 80 95 queues in the slave device, where the least significant bit is queue 80, and most signifi- cant bit is queue 95. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device. name bit pos. type reset description slav_queue_in[79:64] 15:0 rw 0 slave queue indication [79:64]. each bit in this field rep- resents one of the 64 79 queues in the slave device, where the least significant bit is queue 64, and most signifi- cant bit is queue 79. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device. name bit pos. type reset description slav_queue_in[63:48] 15:0 rw 0 slave queue indication [63:48]. each bit in this field rep- resents one of the 48 63 queues in the slave device, where the least significant bit is queue 48, and most signifi- cant bit is queue 63. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device.
agere systems inc. 135 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 110. slave queue 2 (sq2) (016ah) table 111. slave queue 1 (sq1) (016ch) table 112. slave queue 0 (sq0) (016eh) name bit pos. type reset description slav_queue_in[47:32] 15:0 rw 0 slave queue indication [47:32]. each bit in this field rep- resents one of the 32 47 queues in the slave device, where the least significant bit is queue 32, and most signifi- cant bit is queue 47. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device. name bit pos. type reset description slav_queue_in[31:16] 15:0 rw 0 slave queue indication [31:16]. each bit in this field rep- resents one of the 16 31 queues in the slave device, where the least significant bit is queue 16, and most signifi- cant bit is queue 31. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device. name bit pos. type reset description slav_queue_in[15:0] 15:0 rw 0 slave queue indication [15:0]. each bit in this field repre- sents one of the 0 15 queues in the slave device, where the least significant bit is queue 0, and most significant bit is queue 15. these bits indicate which queues in the slave device are enabled for shared utopia mode. if the associ- ated bit is 1, i t indicates to the master that the queue is enabled. these bits are only meaningful in shared utopia mode and must be programmed in the master device.
136 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 113 . tx phy fifo routing 7 (txpfr7) (0170h) name bit pos. type reset description port_rte[127:112] 15:0 rw 0 port route [127:112]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 112 127 queues in the device, where the least significant bit is queue 112, and most significant bit is queue 127. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as fol- lows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-num- bered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208) and in section 11.4, queuing, this register is programmed to 1010101010101010.
agere systems inc. 137 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 114 . tx phy fifo routing 6 (txpfr6) (0172h) name bit pos. type reset description port_rte[111:96] 15:0 rw 0 port route [111:96]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 96 111 queues in the device, where the least significant bit is queue 96, and most significant bit is queue 111. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is config- ured in normal 64-port mode, as described in section 9.2.2, outgo- ing atm mode (cells sent by t8208) and in section 11.4, queuing, this register is programmed to 1010101010101010.
138 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 115 . tx phy fifo routing 5 (txpfr5) (0174h) name bit pos. type reset description port_rte[95:80] 15:0 rw 0 port route [95:80]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 80 95 queues in the device, where the least significant bit is queue 80, and most significant bit is queue 95. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208) and in section 11.4, queuing, this regis- ter is programmed to 1010101010101010.
agere systems inc. 139 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 116 . tx phy fifo routing 4 (txpfr4) (0176h) name bit pos. type reset description port_rte[79:64] 15:0 rw 0 port route [79:64]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 64 79 queues in the device, where the least significant bit is queue 64, and most significant bit is queue 79. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as fol- lows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-num- bered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208) and in section 11.4, queuing, this register is programmed to 1010101010101010.
140 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 117 . tx phy fifo routing 3 (txpfr3) (0178h) name bit pos. type reset description port_rte[63:48] 15:0 rw 0 port route [48:63]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 48 63 queues in the device, where the least significant bit is queue 48, and most significant bit is queue 63. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is config- ured in normal 64-port mode, as described in section 9.2.2, out- going atm mode (cells sent by t8208) and in section 11.4, queuing, this register is programmed to 1010101010101010.
agere systems inc. 141 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 118 . tx phy fifo routing 2 (txpfr2) (017ah) name bit pos. type reset description port_rte[47:32] 15:0 rw 0 port route [32:47]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 32 47 queues in the device, where the least significant bit is queue 32, and most significant bit is queue 47. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208) and in section 11.4, queuing, this regis- ter is programmed to 1010101010101010.
142 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 119 . tx phy fifo routing 1 (txpfr1) (017ch) name bit pos. type reset description port_rte[31:16] 15:0 rw 0 port route [31:16]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 16 31 queues in the device, where the least significant bit is queue 16, and most significant bit is queue 31. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-numbered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208) and in section 11.4, queuing, this regis- ter is programmed to 1010101010101010.
agere systems inc. 143 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 120 . tx phy fifo routing 0 (txpfr0) (017eh) name bit pos. type reset description port_rte[15:0] 15:0 rw 0 port route [15:0]. these port routing bits are only used when 64 phy ports are used. each bit in this field represents one of the 0 15 queues in the device, where the least significant bit is queue 0, and most significant bit is queue 15. these 128 queues are divided into 32 groups of four queues each. the four queues of each group are divided between two phy ports, as follows: group 0queues 0 to 3ports 0 and 1 group 1queues 4 to 7ports 2 and 3 group 2queues 8 to 11ports 4 and 5 group 3queues 12 to 15ports 6 and 7 group 4queues 16 to 19ports 8 and 9 group 5queues 20 to 23ports 10 and 11 group 6queues 24 to 27ports 12 and 13 group 7queues 28 to 31ports 14 and 15 group 8queues 32 to 35ports 16 and 17 group 9queues 36 to 39ports 18 and 19 group 10queues 40 to 43ports 20 and 21 group 11queues 44 to 47ports 22 and 23 group 12queues 48 to 51ports 24 and 25 group 13queues 52 to 55ports 26 and 27 group 14queues 56 to 59ports 28 and 29 group 15queues 60 to 63ports 30 and 31 group 16queues 64 to 67ports 32 and 33 group 17queues 68 to 71ports 34 and 35 group 18queues 72 to 75ports 36 and 37 group 19queues 76 to 79ports 38 and 39 group 20queues 80 to 83ports 40 and 41 group 21queues 84 to 87ports 42 and 43 group 22queues 88 to 91ports 44 and 45 group 23queues 92 to 95ports 46 and 47 group 24queues 96 to 99ports 48 and 49 group 25queues 100 to 103ports 50 and 51 group 26queues 104 to 107ports 52 and 53 group 27queues 108 to 111ports 54 and 55 group 28queues 112 to 115ports 56 and 57 group 29queues 116 to 119ports 58 and 59 group 30queues 120 to 123ports 60 and 61 group 31queues 124 to 127ports 62 and 63 the bits in this field assign each queue in the group to either the odd- or even-numbered phy port in the group. if a bit is cleared to 0, the corresponding queue is assigned to the even-numbered port. if the bit is set to 1, the corresponding queue is assigned to the odd-num- bered port. for 64 phy ports, if the device is configured in normal 64-port mode, as described in section 9.2.2, outgoing atm mode (cells sent by t8208, and in section 11.4, queuing, this register is programmed to 1010101010101010.
144 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 121. global bypass sdram control register (gbscr) (01b0h) name bit pos. type reset description reserved 9:0 ro 0 reserved. program to 0. ovrn_ie 10 rw 0 overrun interrupt enable. an interrupt is generated if this bit and any of the overrun status bits in registers 01c0h01deh are set. the interrupt is generated until this bit or the corre- sponding status bit is reset. reserved 15:11 ro 0 reserved. program to 0.
agere systems inc. 145 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 122. bypass sdram service request register (bssr) (01beh) name bit pos. type reset description queue_serv[7:0] 0 ro 0 queue service[7:0]. this bit represents interrupt status (register 01c0h) of queues 7 to 0 of the tx utopia cell buffer. if this bit is set, at least one of the queues 7 to 0 has interrupt status bits that need servicing. queue_serv[15:8] 1 ro 0 queue service[15:8]. this bit represents interrupt status (register 01c2h) of queues 15 to 8 of the tx utopia cell buffer. if this bit is set, at least one of the queues 15 to 8 has interrupt status bits that need servicing. queue_serv[23:16] 2 ro 0 queue service[23:16]. this bit represents interrupt status (register 01c4h) of queues 23 to 16 of the tx utopia cell buffer. if this bit is set, at least one of the queues 23 to 16 has interrupt status bits that need servicing. queue_serv[31:24] 3 ro 0 queue service[31:24]. this bit represents interrupt status (register 01c6h) of queues 31 to 24 of the tx utopia cell buffer. if this bit is set, at least one of the queues 31 to 24 has interrupt status bits that need servicing. queue_serv[39:32] 4 ro 0 queue service[39:32]. this bit represents interrupt status (register 01c8h) of queues 39 to 32 of the tx utopia cell buffer. if this bit is set, at least one of the queues 39 to 32 has interrupt status bits that need servicing. queue_serv[47:40] 5 ro 0 queue service[47:40]. this bit represents interrupt status (register 01cah) of queues 47 to 40 of the tx utopia cell buffer. if this bit is set, at least one of the queues 47 to 40 has interrupt status bits that need servicing. queue_serv[55:48] 6 ro 0 queue service[55:48]. this bit represents interrupt status (register 01cch) of queues 55 to 48 of the tx utopia cell buffer. if this bit is set, at least one of the queues 55 to 48 has interrupt status bits that need servicing. queue_serv[63:56] 7 ro 0 queue service[63:56]. this bit represents interrupt status (register 01ceh) of queues 63 to 56 of the tx utopia cell buffer. if this bit is set, at least one of the queues 63 to 56 has interrupt status bits that need servicing. queue_serv[71:64] 8 ro 0 queue service[71:64]. this bit represents interrupt status (register 01d0h) of queues 71 to 64 of the tx utopia cell buffer. if this bit is set, at least one of the queues 71 to 64 has interrupt status bits that need servicing. queue_serv[79:72] 9 ro 0 queue service[79:72]. this bit represents interrupt status (register 01d2h) of queues 79 to 72 of the tx utopia cell buffer. if this bit is set, at least one of the queues 79 to 72 has interrupt status bits that need servicing. queue_serv[87:80] 10 ro 0 queue service[87:80]. this bit represents interrupt status (register 01d4h) of queues 87 to 80 of the tx utopia cell buffer. if this bit is set, at least one of the queues 87 to 80 has interrupt status bits that need servicing. queue_serv[95:88] 11 ro 0 queue service[95:88]. this bit represents interrupt status (register 01d6h) of queues 95 to 88 of the tx utopia cell buffer. if this bit is set, at least one of the queues 95 to 88 has interrupt status bits that need servicing.
146 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 122. bypass sdram service request register (bssr) (01beh) (continued) name bit pos. type reset description queue_serv[103:96] 12 ro 0 queue service[103:96]. this bit represents interrupt sta- tus (register 01d8h) of queues 103 to 96 of the tx utopia cell buffer. if this bit is set, at least one of the queues 103 to 96 has interrupt status bits that need servicing. queue_serv[111:104] 13 ro 0 queue service[111:104]. this bit represents interrupt sta- tus (register 01dah) of queues 111 to 104 of the tx uto- pia cell buffer. if this bit is set, at least one of the queues 111 to 104 has interrupt status bits that need servicing. queue_serv[119:112] 14 ro 0 queue service[119:112]. this bit represents interrupt sta- tus (register 01dch) of queues 119 to 112 of the tx uto- pia cell buffer. if this bit is set, at least one of the queues 119 to 112 has interrupt status bits that need servicing. queue_serv[127:120] 15 ro 0 queue service[127:120]. this bit represents interrupt sta- tus (register 01deh) of queues 127 to 120 of the tx uto- pia cell buffer. if this bit is set, at least one of the queues 127 to 120 has interrupt status bits that need servicing.
agere systems inc. 147 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 123. bypass sdram queue interrupt status register 0 (bsqisr0) (01c0h) name bit pos. type reset description reserved 0 ro 0 reserved. q0_ovrn 1 ro 0 queue 0 overrun. this bit is set when queue 0 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q1_ovrn 3 ro 0 queue 1 overrun. this bit is set when queue 1 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q2_ovrn 5 ro 0 queue 2 overrun. this bit is set when queue 2 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q3_ovrn 7 ro 0 queue 3 overrun. this bit is set when queue 3 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q4_ovrn 9 ro 0 queue 4 overrun. this bit is set when queue 4 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q5_ovrn 11 ro 0 queue 5 overrun. this bit is set when queue 5 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q6_ovrn 13 ro 0 queue 6 overrun. this bit is set when queue 6 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q7_ovrn 15 ro 0 queue 7 overrun. this bit is set when queue 7 overruns. an interrupt is generated if the corresponding enable bit is set.
148 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 124. bypass sdram queue interrupt status register 1 (bsqisr1) (01c2h) name bit pos. type reset description reserved 0 ro 0 reserved. q8_ovrn 1 ro 0 queue 8 overrun. this bit is set when queue 8 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q9_ovrn 3 ro 0 queue 9 overrun. this bit is set when queue 9 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q10_ovrn 5 ro 0 queue 10 overrun. this bit is set when queue 10 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q11_ovrn 7 ro 0 queue 11 overrun. this bit is set when queue 11 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q12_ovrn 9 ro 0 queue 12 overrun. this bit is set when queue 12 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q13_ovrn 11 ro 0 queue 13 overrun. this bit is set when queue 13 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q14_ovrn 13 ro 0 queue 14 overrun. this bit is set when queue 14 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q15_ovrn 15 ro 0 queue 15 overrun. this bit is set when queue 15 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 149 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 125. bypass sdram queue interrupt status register 2 (bsqisr2) (01c4h) name bit pos. type reset description reserved 0 ro 0 reserved. q16_ovrn 1 ro 0 queue 16 overrun. this bit is set when queue 16 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q17_ovrn 3 ro 0 queue 17 overrun. this bit is set when queue 17 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q18_ovrn 5 ro 0 queue 18 overrun. this bit is set when queue 18 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q19_ovrn 7 ro 0 queue 19 overrun. this bit is set when queue 19 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q20_ovrn 9 ro 0 queue 20 overrun. this bit is set when queue 20 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q21_ovrn 11 ro 0 queue 21 overrun. this bit is set when queue 21 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q22_ovrn 13 ro 0 queue 22 overrun. this bit is set when queue 22 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q23_ovrn 15 ro 0 queue 23 overrun. this bit is set when queue 23 overruns. an interrupt is generated if the corresponding enable bit is set.
150 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 126. bypass sdram queue interrupt status register 3 (bsqis30) (01c6h) name bit pos. type reset description reserved 0 ro 0 reserved. q24_ovrn 1 ro 0 queue 24 overrun. this bit is set when queue 24 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q25_ovrn 3 ro 0 queue 25 overrun. this bit is set when queue 25 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q26_ovrn 5 ro 0 queue 26 overrun. this bit is set when queue 26 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q27_ovrn 7 ro 0 queue 27 overrun. this bit is set when queue 27 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q28_ovrn 9 ro 0 queue 28 overrun. this bit is set when queue 28 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q29_ovrn 11 ro 0 queue 29 overrun. this bit is set when queue 29 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q30_ovrn 13 ro 0 queue 30 overrun. this bit is set when queue 30 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q31_ovrn 15 ro 0 queue 31 overrun. this bit is set when queue 31 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 151 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 127. bypass sdram queue interrupt status register 4 (bsqisr4) (01c8h) name bit pos. type reset description reserved 0 ro 0 reserved. q32_ovrn 1 ro 0 queue 32 overrun. this bit is set when queue 32 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q33_ovrn 3 ro 0 queue 33 overrun. this bit is set when queue 33 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q34_ovrn 5 ro 0 queue 34 overrun. this bit is set when queue 34 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q35_ovrn 7 ro 0 queue 35 overrun. this bit is set when queue 35 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q36_ovrn 9 ro 0 queue 36 overrun. this bit is set when queue 36 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q37_ovrn 11 ro 0 queue 37 overrun. this bit is set when queue 37 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q38_ovrn 13 ro 0 queue 38 overrun. this bit is set when queue 38 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q39_ovrn 15 ro 0 queue 39 overrun. this bit is set when queue 39 overruns. an interrupt is generated if the corresponding enable bit is set.
152 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 128. bypass sdram queue interrupt status register 5 (bsqisr5) (01cah) name bit pos. type reset description reserved 0 ro 0 reserved. q40_ovrn 1 ro 0 queue 40 overrun. this bit is set when queue 40 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q41_ovrn 3 ro 0 queue 41 overrun. this bit is set when queue 41 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q42_ovrn 5 ro 0 queue 42 overrun. this bit is set when queue 42 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q43_ovrn 7 ro 0 queue 43 overrun. this bit is set when queue 43 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q44_ovrn 9 ro 0 queue 44 overrun. this bit is set when queue 44 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q45_ovrn 11 ro 0 queue 45 overrun. this bit is set when queue 45 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q46_ovrn 13 ro 0 queue 46 overrun. this bit is set when queue 46 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q47_ovrn 15 ro 0 queue 47 overrun. this bit is set when queue 47 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 153 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 129. bypass sdram queue interrupt status register 6 (bsqisr6) (01cch) name bit pos. type reset description reserved 0 ro 0 reserved. q48_ovrn 1 ro 0 queue 48 overrun. this bit is set when queue 48 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q49_ovrn 3 ro 0 queue 49 overrun. this bit is set when queue 49 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q50_ovrn 5 ro 0 queue 50 overrun. this bit is set when queue 50 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q51_ovrn 7 ro 0 queue 51 overrun. this bit is set when queue 51 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q52_ovrn 9 ro 0 queue 52 overrun. this bit is set when queue 52 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q53_ovrn 11 ro 0 queue 53 overrun. this bit is set when queue 53 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q54_ovrn 13 ro 0 queue 54 overrun. this bit is set when queue 54 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q55_ovrn 15 ro 0 queue 55 overrun. this bit is set when queue 55 overruns. an interrupt is generated if the corresponding enable bit is set.
154 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 130. bypass sdram queue interrupt status register 7 (bsqisr7) (01ceh) name bit pos. type reset description reserved 0 ro 0 reserved. q56_ovrn 1 ro 0 queue 56 overrun. this bit is set when queue 56 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q57_ovrn 3 ro 0 queue 57 overrun. this bit is set when queue 57 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q58_ovrn 5 ro 0 queue 58 overrun. this bit is set when queue 58 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q59_ovrn 7 ro 0 queue 59 overrun. this bit is set when queue 59 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q60_ovrn 9 ro 0 queue 60 overrun. this bit is set when queue 60 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q61_ovrn 11 ro 0 queue 61 overrun. this bit is set when queue 61 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q62_ovrn 13 ro 0 queue 62 overrun. this bit is set when queue 62 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q63_ovrn 15 ro 0 queue 63 overrun. this bit is set when queue 63 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 155 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 131. bypass sdram queue interrupt status register 8 (bsqisr8) (01d0h) name bit pos. type reset description reserved 0 ro 0 reserved. q64_ovrn 1 ro 0 queue 64 overrun. this bit is set when queue 64 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q65_ovrn 3 ro 0 queue 65 overrun. this bit is set when queue 65 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q66_ovrn 5 ro 0 queue 66 overrun. this bit is set when queue 66 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q67_ovrn 7 ro 0 queue 67 overrun. this bit is set when queue 67 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q68_ovrn 9 ro 0 queue 68 overrun. this bit is set when queue 68 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q69_ovrn 11 ro 0 queue 69 overrun. this bit is set when queue 69 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q70_ovrn 13 ro 0 queue 70 overrun. this bit is set when queue 70 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q71_ovrn 15 ro 0 queue 71 overrun. this bit is set when queue 71 overruns. an interrupt is generated if the corresponding enable bit is set.
156 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 132. bypass sdram queue interrupt status register 9 (bsqisr9) (01d2h) name bit pos. type reset description reserved 0 ro 0 reserved. q72_ovrn 1 ro 0 queue 72 overrun. this bit is set when queue 72 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q73_ovrn 3 ro 0 queue 73 overrun. this bit is set when queue 73 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q74_ovrn 5 ro 0 queue 74 overrun. this bit is set when queue 74 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q75_ovrn 7 ro 0 queue 75 overrun. this bit is set when queue 75 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q76_ovrn 9 ro 0 queue 76 overrun. this bit is set when queue 76 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q77_ovrn 11 ro 0 queue 77 overrun. this bit is set when queue 77 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q78_ovrn 13 ro 0 queue 78 overrun. this bit is set when queue 78 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q79_ovrn 15 ro 0 queue 79 overrun. this bit is set when queue 79 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 157 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 133. bypass sdram queue interrupt status register 10 (bsqisr10) (01d4h) name bit pos. type reset description reserved 0 ro 0 reserved. q80_ovrn 1 ro 0 queue 80 overrun. this bit is set when queue 80 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q81_ovrn 3 ro 0 queue 81 overrun. this bit is set when queue 81 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q82_ovrn 5 ro 0 queue 82 overrun. this bit is set when queue 82 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q83_ovrn 7 ro 0 queue 83 overrun. this bit is set when queue 83 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q84_ovrn 9 ro 0 queue 84 overrun. this bit is set when queue 84 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q85_ovrn 11 ro 0 queue 85 overrun. this bit is set when queue 85 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q86_ovrn 13 ro 0 queue 86 overrun. this bit is set when queue 86 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q87_ovrn 15 ro 0 queue 87 overrun. this bit is set when queue 87 overruns. an interrupt is generated if the corresponding enable bit is set.
158 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 134. bypass sdram queue interrupt status register 11 (bsqis11) (01d6h) name bit pos. type reset description reserved 0 ro 0 reserved. q88_ovrn 1 ro 0 queue 88 overrun. this bit is set when queue 88 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q89_ovrn 3 ro 0 queue 89 overrun. this bit is set when queue 89 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q90_ovrn 5 ro 0 queue 90 overrun. this bit is set when queue 90 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q91_ovrn 7 ro 0 queue 91 overrun. this bit is set when queue 91 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q92_ovrn 9 ro 0 queue 92 overrun. this bit is set when queue 92 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q93_ovrn 11 ro 0 queue 93 overrun. this bit is set when queue 93 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q94_ovrn 13 ro 0 queue 94 overrun. this bit is set when queue 94 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q95_ovrn 15 ro 0 queue 95 overrun. this bit is set when queue 95 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 159 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 135. bypass sdram queue interrupt status register 12 (bsqisr12) (01d8h) name bit pos. type reset description reserved 0 ro 0 reserved. q96_ovrn 1 ro 0 queue 96 overrun. this bit is set when queue 96 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q97_ovrn 3 ro 0 queue 97 overrun. this bit is set when queue 97 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q98_ovrn 5 ro 0 queue 98 overrun. this bit is set when queue 98 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q99_ovrn 7 ro 0 queue 99 overrun. this bit is set when queue 99 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q100_ovrn 9 ro 0 queue 100 overrun. this bit is set when queue 100 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q101_ovrn 11 ro 0 queue 101 overrun. this bit is set when queue 101 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q102_ovrn 13 ro 0 queue 102 overrun. this bit is set when queue 102 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q103_ovrn 15 ro 0 queue 103 overrun. this bit is set when queue 103 overruns. an interrupt is generated if the corresponding enable bit is set.
160 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 136. bypass sdram queue interrupt status register 13 (bsqisr13) (01dah) name bit pos. type reset description reserved 0 ro 0 reserved. q104_ovrn 1 ro 0 queue 104 overrun. this bit is set when queue 104 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q105_ovrn 3 ro 0 queue 105 overrun. this bit is set when queue 105 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q106_ovrn 5 ro 0 queue 106 overrun. this bit is set when queue 106 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q107_ovrn 7 ro 0 queue 107 overrun. this bit is set when queue 107 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q108_ovrn 9 ro 0 queue 108 overrun. this bit is set when queue 108 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q109_ovrn 11 ro 0 queue 109 overrun. this bit is set when queue 109 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q110_ovrn 13 ro 0 queue 110 overrun. this bit is set when queue 110 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q111_ovrn 15 ro 0 queue 111 overrun. this bit is set when queue 111 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 161 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 137. bypass sdram queue interrupt status register 14 (bsqisr14) (01dch) name bit pos. type reset description reserved 0 ro 0 reserved. q112_ovrn 1 ro 0 queue 112 overrun. this bit is set when queue 112 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q113_ovrn 3 ro 0 queue 113 overrun. this bit is set when queue 113 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q114_ovrn 5 ro 0 queue 114 overrun. this bit is set when queue 114 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q115_ovrn 7 ro 0 queue 115 overrun. this bit is set when queue 115 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q116_ovrn 9 ro 0 queue 116 overrun. this bit is set when queue 116 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q117_ovrn 11 ro 0 queue 117 overrun. this bit is set when queue 117 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q118_ovrn 13 ro 0 queue 118 overrun. this bit is set when queue 118 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q119_ovrn 15 ro 0 queue 119 overrun. this bit is set when queue 119 overruns. an interrupt is generated if the corresponding enable bit is set.
162 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 138. bypass sdram queue interrupt status register 15 (bsqisr15) (01deh) name bit pos. type reset description reserved 0 ro 0 reserved. q120_ovrn 1 ro 0 queue 120 overrun. this bit is set when queue 120 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 2 ro 0 reserved. q121_ovrn 3 ro 0 queue 121 overrun. this bit is set when queue 121 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 4 ro 0 reserved. q122_ovrn 5 ro 0 queue 122 overrun. this bit is set when queue 122 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 6 ro 0 reserved. q123_ovrn 7 ro 0 queue 123 overrun. this bit is set when queue 123 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 8 ro 0 reserved. q124_ovrn 9 ro 0 queue 124 overrun. this bit is set when queue 124 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 10 ro 0 reserved. q125_ovrn 11 ro 0 queue 125 overrun. this bit is set when queue 125 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 12 ro 0 reserved. q126_ovrn 13 ro 0 queue 126 overrun. this bit is set when queue 126 overruns. an interrupt is generated if the corresponding enable bit is set. reserved 14 ro 0 reserved. q127_ovrn 15 ro 0 queue 127 overrun. this bit is set when queue 127 overruns. an interrupt is generated if the corresponding enable bit is set.
agere systems inc. 163 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 139. routing information 1 (ri1) (0200h) name bit pos. type reset description mphy1_sel[5:0] 5:0 rw x multi-phy 1 select [5:0]. the mphy1_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group address bit. mphy2_sel[5:0] 11:6 rw x multi-phy 2 select [5:0]. the mphy2_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group address bit. multi-phy 1 and 2 select [5:0]. the multi-phy select bits are used to determine the queue group to which the cell is directed. the priority select bits are used to determine the queue in the queue group to which the cell is directed. the mphy4_sel[5:0] bits select the most significant bit of the queue group address, and the mphy0_sel[5:0] bits select the least significant bit of the queue group address. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least sig- nificant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significan t bit. the value 110000 is a spe- cial case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
164 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 140. routing information 2 (ri2) (0202h) name bit pos. type reset description reserved_sel[5:0] 5:0 rw x reserved select [5:0]. program these bits to zero. mphy0_sel[5:0] 11:6 rw x multi-phy 0 select [5:0]. the mphy0_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tan- dem routing header is used as this queue group address bit. the multi-phy select bits are used to determine the queue group to which the cell is directed. the priority select bits are used to determine the queue in the queue group to which the cell is directed. the mphy4_sel[5:0] bits select the most significant bit of the queue group address, and the mphy0_sel[5:0] bits select the least significant bit of the queue group address. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
agere systems inc. 165 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 141. routing information 3 (ri3) (0204h) name bit pos. type reset description prior0_sel[5:0] 5:0 rw x priority 0 select. the prior0_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this priority bit. prior1_sel[5:0] 11:6 rw x priority 1 select. the prior1_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this priority bit. priority 0 and 1 select. the multi-phy select bits are used to determine the queue group to which the cell is directed. the priority select bits are used to determine the queue in the queue group to which the cell is directed. the prior1_sel[5:0] bits select the most significant bit of the priority number in the specified group, and the prior0_sel[5:0] bits select the least significant bit of the priority number. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least signif- icant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
166 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 142. ppd information 1 (ppdi1) (0206h) name bit pos. type reset description ppd_pnt12_sel[5:0] 5:0 rw x ppd pointer 12 select. the ppd_pnt12_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tan- dem routing header is used as this offset bit. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 virtual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. ppd_en_sel[5:0] 11:6 rw x ppd enable select. the ppd_en_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this enable bit. the ppd enable select bits are used to identify the aal5 virtual channel and to enable ppd. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem rout- ing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most sig- nificant bit. the val ue 110000 is a special case and may be used to force the value of this bit to 0. if this selected bit in the received cell is one, the partial packet discard feature is enabled. reserved 15:12 ro 0 reserved.
agere systems inc. 167 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 143. ppd information 2 (ppdi2) (0208h) name bit pos. type reset description ppd_pnt10_sel[5:0] 5:0 rw x ppd pointer 10 select. the ppd_pnt10_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd_pnt11_sel[5:0] 11:6 rw x ppd pointer 11 select. the ppd_pnt11_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd pointer 10 and 11 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 virtual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
168 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 144. ppd information 3 (ppdi3) (020ah) name bit pos. type reset description ppd_pnt8_sel[5:0] 5:0 rw x ppd pointer 8 select. the ppd_pnt8_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd_pnt9_sel[5:0] 11:6 rw x ppd pointer 9 select. the ppd_pnt9_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd pointer 8 and 9 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 virtual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
agere systems inc. 169 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 145. ppd information 4 (ppdi4) (020ch) name bit pos. type reset description ppd_pnt6_sel[5:0] 5:0 rw x ppd pointer 6 select. the ppd_pnt6_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd_pnt7_sel[5:0] 11:6 rw x ppd pointer 7 select. the ppd_pnt7_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd pointer 6 and 7 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 vir- tual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significa nt bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
170 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 146. ppd information 5 (ppdi5) (020eh) name bit pos. type reset description ppd_pnt4_sel[5:0] 5:0 rw x ppd pointer 4 select. the ppd_pnt4_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd_pnt5_sel[5:0] 11:6 rw x ppd pointer 5 select. the ppd_pnt5_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd pointer 4 and 5 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 vir- tual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant b it. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
agere systems inc. 171 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 147. ppd information 6 (ppdi6) (0210h) name bit pos. type reset description ppd_pnt2_sel[5:0] 5:0 rw x ppd pointer 2 select. the ppd_pnt2_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd_pnt3_sel[5:0] 11:6 rw x ppd pointer 3 select. the ppd_pnt3_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this offset bit. ppd pointer 2 and 3 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 virtual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
172 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 148. ppd information 7 (ppdi7) (0212h) name bit pos. type reset description ppd_pnt0_sel[5:0] 5:0 rw x ppd pointer 0 select. the ppd_pnt0_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group offset bit. ppd_pnt1_sel[5:0] 11:6 rw x ppd pointer 1 select. the ppd_pnt1_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group offset bit. ppd pointer 0 and 1 select. the ppd pointer select bits are used to create an offset into the ppd state memory. the ppd state memory is used to keep track of aal5 virtual channels for partial packet discard. up to 8192 vir- tual channels may be supported with these select fields. the ppd_pnt12_sel[5:0] bits select the most significant bit of the ppd state memory offset, and the ppd_pnt0_sel[5:0] bits select the least significant bit of the offset. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most signif- icant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least significant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significant bit. the value 110000 is a special case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
agere systems inc. 173 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 149. routing information 4 (ri4) (0214h) name bit pos. type reset description mphy3_sel[5:0] 5:0 rw x multi-phy 3 select [5:0]. the mphy3_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group address bit. mphy4_sel[5:0] 11:6 rw x multi-phy 4 select [5:0]. the mphy4_sel[5:0] bit field selects which bit of the cell header, the cell bus routing header, or the tandem routing header is used as this queue group address bit. multi-phy 3 and 4 select [5:0]. the multi-phy select bits are used to determine the queue group to which the cell is directed. the priority select bits are used to determine the queue in the queue group to which the cell is directed. the mphy4_sel[5:0] bits select the most significant bit of the queue group address, and the mphy0_sel[5:0] bits select the least significant bit of the queue group address. a value of zero to 31 selects bits in the cell header where zero is the clp bit and 31 is the most significant bit of the gfc/vpi field. a value of 32 to 47 selects bits in the tandem routing header where 32 is the least sig- nificant bit and 47 is the most significant bit. a value of 48 to 63 selects bits in the cell bus header where 48 is the least significant bit and 63 is the most significan t bit. the value 110000 is a spe- cial case and may be used to force the value of this bit to 0. if this bit is forced to zero, the bit position in the resultant pointer is always 0 and is not extracted from the received cell. reserved 15:12 ro 0 reserved.
174 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 150. ppd memory write (ppdmw) (0418h) name bit pos. type reset description write_pul 0 rw 0 write pulse. if a '1' is written to this bit, a single bit will be written to the ppd memory. the value of the bit is obtained from the write_val bit, and the address in the ppd memory is obtained from the write_addr bits. the write_pul bit is cleared by hardware when the write is complete. write_val 1 rw 0 write value. this bit contains the value to be written to the ppd state memory bit. write_addr 14:2 rw 0 write address. these bits contain the address of the bit in ppd mem- ory. this address will be used when a write is performed. this address corresponds to the offset from the cell header, cell bus header, and tan- dem routing header as determined from the ppd point select bits. an address of all zeros will point to the most significant bit of word 0, and an address of all ones will point to the least significant bit of word 1ff. reserved 15 ro 0 reserved.
agere systems inc. 175 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.2.2 tx utopia monitoring table 151. phy port x transmit count structure (ppxtxcnt) (0600h to 06feh) name offset type reset description out_cnt_phyx[31:16] 00h rw x outgoing cell count for phy port x [31:16]. the out_cnt_phyx[31:16] and out_cnt_phyx[15:0] fields together are a free- running counter of cells transmitted on utopia phy port x. out_cnt_phyx[15:0] 02h rw x outgoing cell count for phy port x [15:0]. the out_cnt_phyx[31:16] and out_cnt_phyx[15:0] fields together are a free-running counter of cells transmitted on utopia phy port x. the letter x in the data structure name and in the bit names represents the values of 0 through 63 for the 64 phy ports. the base addresses of the 64 data structures are shown below. data structure base address data structure base address phy port 0 transmit count 0 (0600h) phy port 32 transmit count 0 (0680h) phy port 1 transmit count 0 (0604h) phy port 33 transmit count 0 (0684h) phy port 2 transmit count 0 (0608h) phy port 34 transmit count 0 (0688h) phy port 3 transmit count 0 (060ch) phy port 35 transmit count 0 (068ch) phy port 4 transmit count 0 (0610h) phy port 36 transmit count 0 (0690h) phy port 5 transmit count 0 (0614h) phy port 37 transmit count 0 (0694h) phy port 6 transmit count 0 (0618h) phy port 38 transmit count 0 (0698h) phy port 7 transmit count 0 (061ch) phy port 39 transmit count 0 (069ch) phy port 8 transmit count 0 (0620h) phy port 40 transmit count 0 (06a0h) phy port 9 transmit count 0 (0624h) phy port 41 transmit count 0 (06a4h) phy port 10 transmit count 0 (0628h) phy port 42 transmit count 0 (06a8h) phy port 11 transmit count 0 (062ch) phy port 43 transmit count 0 (06ach) phy port 12 transmit count 0 (0630h) phy port 44 transmit count 0 (06b0h) phy port 13 transmit count 0 (0634h) phy port 45 transmit count 0 (06b4h) phy port 14 transmit count 0 (0638h) phy port 46 transmit count 0 (06b8h) phy port 15 transmit count 0 (063ch) phy port 47 transmit count 0 (06bch) phy port 16 transmit count 0 (0640h) phy port 48 transmit count 0 (06c0h) phy port 17 transmit count 0 (0644h) phy port 49 transmit count 0 (06c4h) phy port 18 transmit count 0 (0648h) phy port 50 transmit count 0 (06c8h) phy port 19 transmit count 0 (064ch) phy port 51 transmit count 0 (06cch) phy port 20 transmit count 0 (0650h) phy port 52 transmit count 0 (06d0h) phy port 21 transmit count 0 (0654h) phy port 53 transmit count 0 (06d4h) phy port 22 transmit count 0 (0658h) phy port 54 transmit count 0 (06d8h) phy port 23 transmit count 0 (065ch) phy port 55 transmit count 0 (06dch) phy port 24 transmit count 0 (0660h) phy port 56 transmit count 0 (06e0h) phy port 25 transmit count 0 (0664h) phy port 57 transmit count 0 (06e4h) phy port 26 transmit count 0 (0668h) phy port 58 transmit count 0 (06e8h) phy port 27 transmit count 0 (066ch) phy port 59 transmit count 0 (06ech) phy port 28 transmit count 0 (0670h) phy port 60 transmit count 0 (06f0h) phy port 29 transmit count 0 (0674h) phy port 61 transmit count 0 (06f4h) phy port 30 transmit count 0 (0678h) phy port 62 transmit count 0 (06f8h) phy port 31 transmit count 0 (067ch) phy port 63 transmit count 0 (06fch)
176 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.2.3 rx utopia count monitoring table 152. phy port x receive count structure (ppxrxcnt) (4000h to 40feh) name offset bit pos. type reset description in_cnt_phyx[31:16] 00h 15:0 rw x incoming cell count for phy port x [31:16]. the in_cnt_phyx[31:16] and in_cnt_phyx[15:0] fields together are a free-running counter of cells from phy port x. both valid and misrouted cells are counted. incoming cells are not counted if they encounter an ignore (i) bit in their translation records that is 1 or if their vpi and/or vci are out of range. in_cnt_phyx[15:0] 02h 15:0 incoming cell count for phy port x [15:0]. the in_cnt_phyx[31:16] and in_cnt_phyx[15:0] fields together are a free-running counter of cells from phy port x. both valid and misrouted cells are counted. incoming cells are not counted if they encounter an ignore (i) bit in their translation records that is 1 or if their vpi and/or vci are out of range. the letter x in the data structure name and in the bit names represents the values 0 through 63 for the 64 phy ports. the base addresses of the 64 data structures are shown below. structure name base address structure name base address phy port 0 receive count 0 (4000h) phy port 32 receive count 0 (4080h) phy port 1 receive count 0 (4004h) phy port 33 receive count 0 (4084h) phy port 2 receive count 0 (4008h) phy port 34 receive count 0 (4088h) phy port 3 receive count 0 (400ch) phy port 35 receive count 0 (408ch) phy port 4 receive count 0 (4010h) phy port 36 receive count 0 (4090h) phy port 5 receive count 0 (4014h) phy port 37 receive count 0 (4094h) phy port 6 receive count 0 (4018h) phy port 38 receive count 0 (4098h) phy port 7 receive count 0 (401ch) phy port 39 receive count 0 (409ch) phy port 8 receive count 0 (4020h) phy port 40 receive count 0 (40a0h) phy port 9 receive count 0 (4024h) phy port 41 receive count 0 (40a4h) phy port 10 receive count 0 (4028h) phy port 42 receive count 0 (40a8h) phy port 11 receive count 0 (402ch) phy port 43 receive count 0 (40ach) phy port 12 receive count 0 (4030h) phy port 44 receive count 0 (40b0h) phy port 13 receive count 0 (4034h) phy port 45 receive count 0 (40b4h) phy port 14 receive count 0 (4038h) phy port 46 receive count 0 (40b8h) phy port 15 receive count 0 (403ch) phy port 47 receive count 0 (40bch) phy port 16 receive count 0 (4040h) phy port 48 receive count 0 (40c0h) phy port 17 receive count 0 (4044h) phy port 49 receive count 0 (40c4h) phy port 18 receive count 0 (4048h) phy port 50 receive count 0 (40c8h) phy port 19 receive count 0 (404ch) phy port 51 receive count 0 (40cch) phy port 20 receive count 0 (4050h) phy port 52 receive count 0 (40d0h) phy port 21 receive count 0 (4054h) phy port 53 receive count 0 (40d4h) phy port 22 receive count 0 (4058h) phy port 54 receive count 0 (40d8h) phy port 23 receive count 0 (405ch) phy port 55 receive count 0 (40dch) phy port 24 receive count 0 (4060h) phy port 56 receive count 0 (40e0h) phy port 25 receive count 0 (4064h) phy port 57 receive count 0 (40e4h) phy port 26 receive count 0 (4068h) phy port 58 receive count 0 (40e8h) phy port 27 receive count 0 (406ch) phy port 59 receive count 0 (40ech) phy port 28 receive count 0 (4070h) phy port 60 receive count 0 (40f0h) phy port 29 receive count 0 (4074h) phy port 61 receive count 0 (40f4h) phy port 30 receive count 0 (4078h) phy port 62 receive count 0 (40f8h) phy port 31 receive count 0 (407ch) phy port 63 receive count 0 (40fch)
agere systems inc. 177 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.2.4 rx utopia configuration monitoring table 153. phy port x configuration structure (ppxcf) (4200h to 42feh) name offset bit pos. type reset description lutx_vpi_base 00h 15:0 rw x phy port x vpi base address. these bits define bits 3 through 18 of the vpi base address offset in the look-up table for phy port x. the offset may be a maximum of 19 bits. if 16-byte records are used, the least significant bit of this word is ignored. lutx_vpi_mask 02h 11:0 phy port x vpi mask. this 12-bit field is used to mask the incoming vpi bits. if a bit in the field is set to 1, the value of the corresponding bit in the incoming vpi will be mean- ingful. all other bits of the incoming vpi will be forced to zero. lutx_vpi_chk 12 phy port x vpi check. if this bit is set to 1, the unused incoming vpi bits must be 0, or the cell will be counted as misrouted. unused bits are bits whose corresponding lutx_vpi_mask bit equal zero. lutx_uni_en 13 phy port x user network interface (uni) enable. if this bit is set to 1, the port is identified as uni, and the gfc field of the cell header will not be used in the look-up table. if this bit is 0, the port is identified as nni. reserved 15:14 reserved. the letter x in the data structure name and in the bit names represents the values 0 through 63 for the 64 phy ports. the base addresses of the 64 data structures are shown below. structure name base address structure name base address phy port 0 configuration (4200h) phy port 21 configuration (4254h) phy port 1 configuration (4204h) phy port 22 configuration (4258h) phy port 2 configuration (4208h) phy port 23 configuration (425ch) phy port 3 configuration (420ch) phy port 24 configuration (4260h) phy port 4 configuration (4210h) phy port 25 configuration (4264h) phy port 5 configuration (4214h) phy port 26 configuration (4268h) phy port 6 configuration (4218h) phy port 27 configuration (426ch) phy port 7 configuration (421ch) phy port 28 configuration (4270h) phy port 8 configuration (4220h) phy port 29 configuration (4274h) phy port 9 configuration (4224h) phy port 30 configuration (4278h) phy port 10 configuration (4228h) phy port 31 configuration (427ch) phy port 11 configuration (422ch) phy port 32 configuration (4280h) phy port 12 configuration (4230h) phy port 33 configuration (4284h) phy port 13 configuration (4234h) phy port 34 configuration (4288h) phy port 14 configuration (4238h) phy port 35 configuration (428ch) phy port 15 configuration (423ch) phy port 36 configuration (4290h) phy port 16 configuration (4240h) phy port 37 configuration (4294h) phy port 17 configuration (4244h) phy port 38 configuration (4298h) phy port 18 configuration (4248h) phy port 39 configuration (429ch) phy port 19 configuration (424ch) phy port 40 configuration (42a0h) phy port 20 configuration (4250h) phy port 41 configuration (42a4h)
178 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 153. phy port x configuration structure (ppxcf) (4200h to 42feh) (continued) structure name base address structure name base address phy port 42 configuration (42a8h) phy port 53 configuration (42d4h) phy port 43 configuration (42ach) phy port 54 configuration (42d8h) phy port 44 configuration (42b0h) phy port 55 configuration (42dch) phy port 45 configuration (42b4h) phy port 56 configuration (42e0h) phy port 46 configuration (42b8h) phy port 57 configuration (42e4h) phy port 47 configuration (42bch) phy port 58 configuration (42e8h) phy port 48 configuration (42c0h) phy port 59 configuration (42ech) phy port 49 configuration (42c4h) phy port 60 configuration (42f0h) phy port 50 configuration (42c8h) phy port 61 configuration (42f4h) phy port 51 configuration (42cch) phy port 62 configuration (42f8h) phy port 52 configuration (42d0h) phy port 63 configuration (42fch)
agere systems inc. 179 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.3 sdram registers table 154. sdram control (sct) (0400h) table 155. sdram interrupt status (sis) (0402h) table 156. sdram interrupt enable (sie) (0404h) name bit pos. type reset description sdram_en 0 rw 0 sdram enable. if th is bit is set to 1, th e sdram becomes activ e. if 0, the sdram is in the idle state. gen_man_acc 1 wo 0 generate manual access. if the sdram_en bit is 0, writing a 1 to this bit will take the sdram out of its idle state and activate the manual values programmed in the cas_man, ras_man, we_man, bs_man, and addr_man bits. the 1 pulses for one clock cycle and clears to 0 automatically. the sdram then returns to its idle state. this special mode is used in the start-up sequence for the sdram. reserved 14:2 ro 0 reserved. reserved 15 rw 0 reserved. program this bit to 0. name bit pos. type reset description ref_late 0 rol 0 refresh late. this bit is set when the refresh cycle for the sdram is greater than the value programmed in the late_lim bits. an interrupt is generated if the corresponding enable bit is set. crc8_err_even 1 rol 0 crc8 error on even data byte. this bit is set when an error is detected on the even byte (sd_d[15:8]) of the sdram data bus. an interrupt is generated if the corresponding enable bit is set. crc8_err_odd 2 rol 0 crc8 error on odd data byte. this bit is set when an error is detected on the odd byte (sd_d[7:0]) of the sdram data bus. an interrupt is generated if the corresponding enable bit is set. reserved 15:3 ro 0 reserved. name bit pos. type reset description ref_late_ie 0 rw 0 refresh late interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gen- erated until this bit or the corresponding status bit is reset. crc8_err_even_ie 1 rw 0 crc8 error on even data byte interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding sta- tus bit is reset. crc8_err_odd_ie 2 rw 0 crc8 error on odd data byte interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset. reserved 15:3 ro 0 reserved.
180 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 157. sdram configuration (scf) (0408h) name bit pos. type reset description col_num 1:0 rw 0 column number. these bits are used to indicate the number of col- umns in the sdram. 100 = 256 columns 0 1 = 512 columns 1 0 = 1024 columns 1 1 = reserved cas_lat 2 rw 0 cas latency. this bit is used to indicate the cas latency of the sdram based on the clock frequency and speed grade of the device. 0 = 2 cycles 1 = 3 cycles ras2cas 4:3 rw 2h ras inactive to cas active delay. these bits specify the minimum time in sdram clock cycles from ras going inactive to cas going active. 0 1 = 2 clock cycles 1 0 = 2 clock cycles 1 1 = 3 clock cycles 0 0 = 4 clock cycles cas2pre 6:5 rw 1 cas inactive to precharge active delay. these bits specify the min- imum time in sdram clock cycles from cas going inactive to the pre- charge command going active. 0 1 = 1 clock cycles 1 0 = 2 clock cycles 1 1 = 3 clock cycles 0 0 = 4 clock cycles pre2cmd 8:7 rw 2h precharge inactive to next command active delay. these bits specify the minimum time in sdram clock cycles from the precharge command going inactive to next command going active. 0 1 = 1 clock cycles 1 0 = 2 clock cycles 1 1 = 3 clock cycles 0 0 = 4 clock cycles ref2cmd 10:9 rw 0 cbr refresh inactive to next command active delay. these bits specify the minimum time in sdram clock cycles from the refresh command going inactive to next refresh command going active. 0 0 = 15 clock cycles 0 1 = reserved 1 0 = 3 clock cycles 1 1 = 7 clock cycles reserved 15:11 ro 0 reserved.
agere systems inc. 181 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 158. refresh (rfrsh) (0410h) table 159. refresh lateness (rfrshl) (0412h) table 160. idle state 1 (is1) (0420h) table 161. idle state 2 (is2) (0422h) name bit pos. type reset description ref_cnt 15:0 rw 0400h refresh count. these bits are used to program the refresh cycle in sdram clock cycles. the number of clock cycles programmed in this register should be less than one half the worst-case refresh period. name bit pos. type reset description late_lim 15:0 rw 0400h lateness limit. these bits are used to program how late a refresh cycle may occur. this limit is in refresh cycles. when this limit is reached, the ref_late status bit will be set. name bit pos. type reset description cas_idle 0 rw 1 sdram cas idle value. this is the value that will be placed on the sd_cas* pin while the sdram is idle (sdram_en = 0). ras_idle 1 rw 1 sdram ras idle value. this is the value that will be placed on the sd_ras* pin while the sdram is idle (sdram_en = 0). we_idle 2 rw 1 sdram write enable idle value. this is the value that will be placed on the sd_we* pin while the sdram is idle (sdram_en = 0). bs_idle[1:0] 4:3 rw 3h sdram bank select idle value. this is the value that will be placed on the sd_bs[1:0] pins while the sdram is idle (sdram_en = 0). reserved 15:5 ro 0 reserved. name bit pos. type reset description addr_idle[11:0] 11:0 rw 0 sdram address idle value. this is the value that will be placed on the sd_a[11:0] pins while the sdram is idle (sdram_en = 0). reserved 15:12 ro 0 reserved.
182 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 162. manual access state 1 (mas1) (0424h) table 163. manual access state 2 (mas2) (0426h) name bit pos. type reset description cas_ man 0 rw 1 sdram cas manual value. this is the value that will be placed on the sd_cas* pin for one clock cycle when the gen_man_acc bit is written to 1. ras_ man 1 rw 1 sdram ras manual value. this is the value that will be placed on the sd_ras* pin for one clock cycle when the gen_man_acc bit is written to 1. we_ man 2 rw 1 sdram write enable manual value. this is the value that will be placed on the sd_we* pin for one clock cycle when the gen_man_acc bit is written to 1. bs_ man[1:0] 4:3 rw 3h sdram band select manual value. this is the value that will be placed on the sd_bs[1:0] pins for one clock cycle when the gen_man_acc bit is written to 1. reserved 15:5 ro 0 reserved. name bit pos. type reset description addr_man[11:0] 11:0 rw 0 sdram address manual value. this is the value that will be placed on the sd_ a[11:0] pins for one clock cycle when the gen_man_acc bit is written to 1. reserved 15:12 ro 0 reserved.
agere systems inc. 183 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 164. sdram interrupt service request 7 (sisr7) (0430h) table 165. sdram interrupt service request 6 (sisr6) (0432h) table 166. sdram interrupt service request 5 (sisr5) (0434h) table 167. sdram interrupt service request 4 (sisr4) (0436h) name bit pos. type reset description queue_serv[127:112] 15:0 ro 0 queue service [127:112]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 112 register. if the corresponding bit is 1, the specific queue register has inter- rupt status bits that need servicing. name bit pos. type reset description queue_serv [111:96] 15:0 ro 0 queue service [111:96]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 96 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing. name bit pos. type reset description queue_serv [95:80] 15:0 ro 0 queue service [95:80]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 80 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing. name bit pos. type reset description queue_serv [79:64] 15:0 ro 0 queue service [79:64]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 64 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing.
184 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 168. sdram interrupt service request 3 (sisr3) (0438h) table 169. sdram interrupt service request 2 (sisr2) (043ah) table 170. sdram interrupt service request 1 (sisr1) (043ch) table 171. sdram interrupt service request 0 (sisr0) (043eh) name bit pos. type reset description queue_serv[63:48] 15:0 ro 0 queue service [63:48]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 48 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing. name bit pos. type reset description queue_serv [47:32] 15:0 ro 0 queue service [47:32]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 32 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing. name bit pos. type reset description queue_serv [31:16] 15:0 ro 0 queue service [31:16]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 16 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing. name bit pos. type reset description queue_serv [15:0] 15:0 ro 0 queue service [15:0]. each bit in this field represents one of 16 queue x registers from the 128 queue x registers. the least significant bit represents the queue 0 register. if the cor- responding bit is 1, the specific queue register has interrupt status bits that need servicing.
agere systems inc. 185 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 172. queue x (qx) (0440h to 053eh) name bit pos. type reset description queuex_rd_en 0 rw 0 queue x read enable. if this bit is 1, the queue is enabled for read operations. when any configuration bits are changed, this bit must be 0. note: to prevent corruption of data, this bit must be cleared in unused queues. queuex_wr_en 1 rw 0 queue x write enable. if this bit is 1, the queue is enabled for write operations. when any configuration bits are changed, this bit must be 0. note: to prevent corruption of data, this bit must be cleared in unused queues. queuex_fecn_en 2 rw 0 queue x fecn enable. if this bit is 1, the forward explicit con- gestion notification (fecn) feature is enabled. queuex_clp_en 3 rw 0 queue x clp enable. if this bit is 1, the cell loss priority (clp) feature is enabled. reserved 7:4 ro 0 reserved. queuex_fecn_lim 8 rol 0 queue x fecn limit reached. this bit is set when the fecn limit has been reached in the queue. an interrupt is generated if the corresponding enable bit is set. queuex_clp_lim 9 rol 0 queue x clp limit reached. this bit is set when the clp limit has been reached in the queue. an interrupt is generated if the corresponding enable bit is set. queuex_ovrn 10 rol 0 queue x overrun. this bit is set when the queue overruns. an interrupt is generated if the corresponding enable bit is set. queuex_emp 11 rol 0 queue x empty. this bit is set when the queue is empty. an interrupt is generated if the corresponding enable bit is set. queuex_fecn_lim_ie 12 rw 0 queue x fecn limit reached interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding sta- tus bit is reset. queuex_clp_lim_ie 13 rw 0 queue x clp limit reached interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding sta- tus bit is reset. queuex_ovrn_ie 14 rw 0 queue x overrun interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is generated until this bit or the corresponding status bit is reset.
186 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 172. queue x (qx) (0440h to 053eh) (continued) name bit pos. type reset description queuex_emp_ie 15 rw 0 queue x empty interrupt enable. an interrupt is generated if this bit and the corresponding status bit are set. the interrupt is gener- ated until this bit or the corresponding status bit is reset. the letter x in the register name and in the bit names represents the values of 0 through 127 for the 128 queues shown below. register name register address register name register address register name register address register name register address queue 0 (q0) (0440h) queue 32 (q32) (0480h) queue 64 (q64) (04c0h) queue 96 (q96) (0500h) queue 1 (q1) (0442h) queue 33 (q33) (0482h) queue 65 (q65) (04c2h) queue 97 (q97) (0502h) queue 2 (q2) (0444h) queue 34 (q34) (0484h) queue 66 (q66) (04c4h) queue 98 (q98) (0504h) queue 3 (q3) (0446h) queue 35 (q35) (0486h) queue 67 (q67) (04c6h) queue 99 (q99) (0506h) queue 4 (q4) (0448h) queue 36 (q36) (0488h) queue 68 (q68) (04c8h) queue 100 (q100) (0508h) queue 5 (q5) (044ah) queue 37 (q37) (048ah) queue 69 (q69) (04cah) queue 101 (q101) (050ah) queue 6 (q6) (044ch) queue 38 (q38) (048ch) queue 70 (q70) (04cch) queue 102 (q102) (050ch) queue 7 (q7) (044eh) queue 39 (q39) (048eh) queue 71 (q71) (04ceh) queue 103 (q103) (050eh) queue 8 (q8) (0450h) queue 40 (q40) (0490h) queue 72 (q72) (04d0h) queue 104 (q104) (0510h) queue 9 (q9) (0452h) queue 41 (q41) (0492h) queue 73 (q73) (04d2h) queue 105 (q105) (0512h) queue 10 (q10) (0454h) queue 42 (q42) (0494h) queue 74 (q74) (04d4h) queue 106 (q106) (0514h) queue 11 (q11) (0456h) queue 43 (q43) (0496h) queue 75 (q75) (04d6h) queue 107 (q107) (0516h) queue 12 (q12) (0458h) queue 44 (q44) (0498h) queue 76 (q76) (04d8h) queue 108 (q108) (0518h) queue 13 (q13) (045ah) queue 45 (q45) (049ah) queue 77 (q77) (04dah) queue 109 (q109) (051ah) queue 14 (q14) (045ch) queue 46 (q46) (049ch) queue 78 (q78) (04dch) queue 110 (q110) (051ch) queue 15 (q15) (045eh) queue 47 (q47) (049eh) queue 79 (q79) (04deh) queue 111 (q111) (051eh) queue 16 (q16) (0460h) queue 48 (q48) (04a0h) queue 80 (q80) (04e0h) queue 112 (q112) (0520h) queue 17 (q17) (0462h) queue 49 (q49) (04a2h) queue 81 (q81) (04e2h) queue 113 (q113) (0522h) queue 18 (q18) (0464h) queue 50 (q50) (04a4h) queue 82 (q82) (04e4h) queue 114 (q114) (0524h) queue 19 (q19) (0466h) queue 51 (q51) (04a6h) queue 83 (q83) (04e6h) queue 115 (q115) (0526h) queue 20 (q20) (0468h) queue 52 (q52) (04a8h) queue 84 (q84) (04e8h) queue 116 (q116) (0528h) queue 21 (q21) (046ah) queue 53 (q53) (04aah) queue 85 (q85) (04eah) queue 117 (q117) (052ah) queue 22 (q22) (046ch) queue 54 (q54) (04ach) queue 86 (q86) (04ech) queue 118 (q118) (052ch) queue 23 (q23) (046eh) queue 55 (q55) (04aeh) queue 87 (q87) (04eeh) queue 119 (q119) (052eh) queue 24 (q24) (0470h) queue 56 (q56) (04b0h) queue 88 (q88) (04f0h) queue 120 (q120) (0530h) queue 25 (q25) (0472h) queue 57 (q57) (04b2h) queue 89 (q89) (04f2h) queue 121 (q121) (0532h) queue 26 (q26) (0474h) queue 58 (q58) (04b4h) queue 90 (q90) (04f4h) queue 122 (q122) (0534h) queue 27 (q27) (0476h) queue 59 (q59) (04b6h) queue 91 (q91) (04f6h) queue 123 (q123) (0536h) queue 28 (q28) (0478h) queue 60 (q60) (04b8h) queue 92 (q92) (04f8h) queue 124 (q124) (0538h) queue 29 (q29) (047ah) queue 61 (q61) (04bah) queue 93 (q93) (04fah) queue 125 (q125) (053ah) queue 30 (q30) (047ch) queue 62 (q62) (04bch) queue 94 (q94) (04fch) queue 126 (q126) (053ch) queue 31 (q31) (047eh) queue 63 (q63) (04beh) queue 95 (q95) (04feh) queue 127 (q127) (053eh)
agere systems inc. 187 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.3.1 sdram control memory table 173. queue x definition structure (qxdef) (2000h to 2ffeh) name offset bit pos. type reset description base_addrx[24:9] 00h 15:0 rw x base address queue x [24:9]. these bits configure the upper 16 bits of the queues base address in increments of one cell (64 bytes). base_addrx[8:6] 02h 15:13 rw base address queue x [8:6]. these bits configure bits 6 through 8 of the queues base address offset in increments of one cell (64 bytes). reserved 12:0 ro reserved. end_addrx[24:9] 04h 15:0 rw end address queue x [24:9]. these bits configure the upper 16 bits of the queues end address in increments of one cell. the total number of cells held by the queue may be calculated by subtracting the base_addr from the end_addr and adding one to the difference. the minimum size of any queue is four cells. end_addrx[8:6] 06h 15:13 rw end address queue x [8:6]. these bits configure bits 6 through 8 of the queues end address in increments of one cell. the total number of cells held by the queue may be calculated by subtracting the base_addr from the end_addr and adding one to the difference. the minimum size of any queue is four cells. reserved 12:0 ro reserved. wr_pntx[24:9] 08h 15:0 rw write pointer for queue x [24:9]. these bits must be initial- ized to the base_addrx[24:9] before the queue is enabled. wr_pntx[8:6] 0ah 15:13 rw write pointer for queue x [8:6]. these bits must be initialized to the base_addrx[8:6] before the queue is enabled. reserved 12:0 ro reserved. rd_pntx[24:9] 0ch 15:0 rw read pointer for queue x [24:9]. these bits must be initial- ized to the base_addrx[24:9] before the queue is enabled. rd_pntx[8:6] 0eh 15:13 rw read pointer for queue x [8:6]. these bits must be initialized to the base_addrx[8:6] before the queue is enabled. reserved 12:0 ro reserved. fecn_fillx[24:9] 10h 15:0 rw x fecn fill for queue x [24:9]. these bits with fecn_fillx[8:6] determine the queues fill level in cells (64 bytes) where the fecn bit is set in outgoing cells. the fecn bit is set only when the queuex_fecn_en bit is 1. fecn_fillx[8:6] 12h 15:13 rw fecn fill for queue x [8:6]. these bits with fecn_fillx[24:9] determine the queues fill level in cells (64 bytes) where the fecn bit is set in outgoing cells. the fecn bit is set only when the queuex_fecn_en bit is 1. reserved 12:0 ro reserved. clp_fillx[24:9] 14h 15:0 rw clp fill for queue x [24:9]. these bits with clp_fillx[8:6] determine the queues fill level in cells (64 bytes) where incom- ing cells with their clp bit set will be discarded. the incoming cell is dropped at this fill level only when the queuex_clp_en bit is 1. clp_fillx[8:6] 16h 15:13 rw clp fill for queue x [8:6]. these bits with clp_fillx[24:9] determine the queues fill level in cells (64 bytes) where incom- ing cells with their clp bit set will be discarded. the incoming cell is dropped at this fill level only when the queuex_clp_en bit is 1. reserved 12:0 ro reserved.
188 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 173. queue x definition structure (qxdef) (2000h to 2ffeh) (continued) name offset bit pos. type reset description the letter x in the data structure name and in the bit names represents the values of 0 through 127 for the 128 queues shown below. structure name base address structure name base address queue 0 base address high (2000h) queue 32 base address high (2400h) queue 1 base address high (2020h) queue 33 base address high (2420h) queue 2 base address high (2040h) queue 34 base address high (2440h) queue 3 base address high (2060h) queue 35 base address high (2460h) queue 4 base address high (2080h) queue 36 base address high (2480h) queue 5 base address high (20a0h) queue 37 base address high (24a0h) queue 6 base address high (20c0h) queue 38 base address high (24c0h) queue 7 base address high (20e0h) queue 39 base address high (24e0h) queue 8 base address high (2100h) queue 40 base address high (2500h) queue 9 base address high (2120h) queue 41 base address high (2520h) queue 10 base address high (2140h) queue 42 base address high (2540h) queue 11 base address high (2160h) queue 43 base address high (2560h) queue 12 base address high (2180h) queue 44 base address high (2580h) queue 13 base address high (21a0h) queue 45 base address high (25a0h) queue 14 base address high (21c0h) queue 46 base address high (25c0h) queue 15 base address high (21e0h) queue 47 base address high (25e0h) queue 16 base address high (2200h) queue 48 base address high (2600h) queue 17 base address high (2220h) queue 49 base address high (2620h) queue 18 base address high (2240h) queue 50 base address high (2640h) queue 19 base address high (2260h) queue 51 base address high (2660h) queue 20 base address high (2280h) queue 52 base address high (2680h) queue 21 base address high (22a0h) queue 53 base address high (26a0h) queue 22 base address high (22c0h) queue 54 base address high (26c0h) queue 23 base address high (22e0h) queue 55 base address high (26e0h) queue 24 base address high (2300h) queue 56 base address high (2700h) queue 25 base address high (2320h) queue 57 base address high (2720h) queue 26 base address high (2340h) queue 58 base address high (2740h) queue 27 base address high (2360h) queue 59 base address high (2760h) queue 28 base address high (2380h) queue 60 base address high (2780h) queue 29 base address high (23a0h) queue 61 base address high (27a0h) queue 30 base address high (23c0h) queue 62 base address high (27c0h) queue 31 base address high (23e0h) queue 63 base address high (27e0h)
agere systems inc. 189 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 173. queue x definition structure (qxdef) (2000h to 2ffeh) (continued) name offset bit pos. type reset description the letter x in the data structure name and in the bit names represents the values of 0 through 127 for the 128 queues shown below. structure name base address structure name base address queue 64 base address high (2800h) queue 96 base address high (2c00h) queue 65 base address high (2820h) queue 97 base address high (2c20h) queue 66 base address high (2840h) queue 98 base address high (2c40h) queue 67 base address high (2860h) queue 99 base address high (2c60h) queue 68 base address high (2880h) queue 100 base address high (2c80h) queue 69 base address high (28a0h) queue 101 base address high (2ca0h) queue 70 base address high (28c0h) queue 102 base address high (2cc0h) queue 71 base address high (28e0h) queue 103 base address high (2ce0h) queue 72 base address high (2900h) queue 104 base address high (2d00h) queue 73 base address high (2920h) queue 105 base address high (2d20h) queue 74 base address high (2940h) queue 106 base address high (2d40h) queue 75 base address high (2960h) queue 107 base address high (2d60h) queue 76 base address high (2980h) queue 108 base address high (2d80h) queue 77 base address high (29a0h) queue 109 base address high (2da0h) queue 78 base address high (29c0h) queue 110 base address high (2dc0h) queue 79 base address high (29e0h) queue 111 base address high (2de0h) queue 80 base address high (2a00h) queue 112 base address high (2e00h) queue 81 base address high (2a20h) queue 113 base address high (2e20h) queue 82 base address high (2a40h) queue 114 base address high (2e40h) queue 83 base address high (2a60h) queue 115 base address high (2e60h) queue 84 base address high (2a80h) queue 116 base address high (2e80h) queue 85 base address high (2aa0h) queue 117 base address high (2ea0h) queue 86 base address high (2ac0h) queue 118 base address high (2ec0h) queue 87 base address high (2ae0h) queue 119 base address high (2ee0h) queue 88 base address high (2b00h) queue 120 base address high (2f00h) queue 89 base address high (2b20h) queue 121 base address high (2f20h) queue 90 base address high (2b40h) queue 122 base address high (2f40h) queue 91 base address high (2b60h) queue 123 base address high (2f60h) queue 92 base address high (2b80h) queue 124 base address high (2f80h) queue 93 base address high (2ba0h) queue 125 base address high (2fa0h) queue 94 base address high (2bc0h) queue 126 base address high (2fc0h) queue 95 base address high (2be0h) queue 127 base address high (2fe0h)
190 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.4 various internal memories 14.3.4.1 control cell memories table 174. control cell receive extended memory (ccrxem) (07fch to 0832h) the control cell receive memory may also be accessed from direct memory. see table 51. table 175. control cell transmit extended memory (cctxem) (0900h to 0936h) the control cell transmit memory may also be accessed from direct memory. see table 52. name offset type reset description cell_bus_routing_header 0 ro x these 56 bytes are the control cell received from the cell bus. when present, the control cell may be read from this extended memory space. tandem_routing_header 2 header[31:16] 4 header[15:0] 6 payload_bytes 01 8 . . . . . . payload_bytes 4647 36h name offset type reset description cell_bus_routing_header 0 rw x these 56 bytes are the cell routing header, the tandem rout- ing header, and the control cell to be transmitted onto the cell bus. a control cell to be transmitted may be written to this extended memory space. tandem_routing_header 2 header[31:16] 4 header[15:0] 6 payload_bytes 01 8 . . . . . . payload_bytes 4647 36h
agere systems inc. 191 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.4.2 multicast number memories table 176. phy port 0 and control cells multicast extended memory (pp0mem) (0c00h to 0c1eh) the phy port 0 and control cells multicast memory may also be accessed from direct memory (see table 53). name offset type reset description multicast_receive_enable[15:0] 00h rw x this memory space contains 256 active-high enable bits. each bit represents a multicast net number from 0 through 255. if a bit is set, the corre- sponding multicast net number data cell is sent to the queue group for phy port 0, or the correspond- ing multicast control cell is sent to the control cell receive direct and extended memory. the least sig- nificant bit is multicast net number 0. multicast_receive_enable[31:16] 02h multicast_receive_enable[47:32] 04h . . . . . . multicast_receive_enable[191:176] 16h multicast_receive_enable[207:192] 18h multicast_receive_enable[223:208] 1ah multicast_receive_enable[239:224] 1ch multicast_receive_enable[255:240] 1eh
192 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 177. phy port x multicast memory (ppxmm) (0c20h to 0ffeh) name offset type reset description multicast_receive_enable[15:0] 00h rw x this memory space contains 256 active-high enable bits. each bit represents a multicast net number from 0 through 255. if a bit is set, the corresponding multi- cast net number data cell is sent to the queue group for phy port x. the least significant bit is multicast net number 0. multicast_receive_enable[31:16] 02h multicast_receive_enable[47:32] 04h . . . . . . multicast_receive_enable[239:224] 1ch multicast_receive_enable[255:240] 1eh the letter x in the data structure and in the bit names represents the values of 1 through 31 for 31 of the 32 phy ports. the base addresses of the 31 multicast memory locations are shown below. memory name base address phy port 1 multicast memory (0c20h) phy port 2 multicast memory (0c40h) phy port 3 multicast memory (0c60h) phy port 4 multicast memory (0c80h) phy port 5 multicast memory (0ca0h) phy port 6 multicast memory (0cc0h) phy port 7 multicast memory (0ce0h) phy port 8 multicast memory (0d00h) phy port 9 multicast memory (0d20h) phy port 10 multicast memory (0d40h) phy port 11 multicast memory (0d60h) phy port 12 multicast memory (0d80h) phy port 13 multicast memory (0da0h) phy port 14 multicast memory (0dc0h) phy port 15 multicast memory (0de0h) phy port 16 multicast memory (0e00h) phy port 17 multicast memory (0e20h) phy port 18 multicast memory (0e40h) phy port 19 multicast memory (0e60h) phy port 20 multicast memory (0e80h) phy port 21 multicast memory (0ea0h) phy port 22 multicast memory (0ec0h) phy port 23 multicast memory (0ee0h) phy port 24 multicast memory (0f00h) phy port 25 multicast memory (0f20h) phy port 26 multicast memory (0f40h) phy port 27 multicast memory (0f60h) phy port 28 multicast memory (0f80h) phy port 29 multicast memory (0fa0h) phy port 30 multicast memory (0fc0h) phy port 31 multicast memory (0fe0h)
agere systems inc. 193 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.4.3 ppd state memory table 178. ppd memory (ppdm) (1000h to 13feh) name offset type reset description word0 00h rw x this memory space contains 8192 aal5 virtual channel ppd bits. the ppd pointer bits in the cell header, cell bus routing header, and tandem routing header, which are selected by the ppd pointer select bits, point to a single bit in this memory space. if the bit for a corresponding aal5 virtual channel is 0, no cells are dropped. if the bit is 1, all remaining cells in the packet, except the last cell, are dropped. a ppd bit becomes set when a cell in an aal5 virtual channel packet is dropped. the last cell of a packet is identified by the least significant bit of the pti field in the cell header, which is set to 1. the most significant bit of the pti field is also checked to be 0 (user data). the final cell of the packet is sent, and the corresponding ppd bit is cleared. the most significant bit of word0 corresponds to aal5 virtual channel zero, and the least signifi- cant bit of word1ff corresponds to aal5 virtual channel 8191. word1 02h word2 04h word3 06h word4 08h word5 0ah word6 0ch word7 0eh . . . . . . word1f9 3f2h word1fa 3f4h word1fb 3f6h word 1fc 3f8h word1fd 3fah word1fe 3fch word1ff 3feh
194 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.5 dropped cell count these registers count only cells dropped on sdram or tx utopia cell buffer (256 cells). they cannot count cells dropped at tx phy fifo. table 179. queue x dropped cell count (qxdcc) (3000h to 31feh) name offset bit pos. type reset description queuex_drop_cell_cnt[23:16] 00h 7:0 rw 0 queue x drop cell count[23:16]. the queuex_drop_cell_cnt[23:16] and queuex_drop_cell_cnt[15:0] fields together are a free-running counter of cells dropped on queue x of the sdram or tx utopia cell buffer. queuex_drop_cell_ovrfl[23:16] 00h 8 rw 0 queue x drop cell counter overflow. if this bit is set to 1 by the t8208 logic, it indicates that the dropped cell counter for queue x has overflowed. once this bit is set, it stays set until it is cleared by the customer (this bit is cleared automatically after a read operation if clear_on_read, bit 12 in register 0112h is set to 1). if this bit is 0, it indicates that the dropped cell counter for queue x has not overflowed. queuex_drop_clp0_cell_dis 00h 9 rw 0 queue x clp0 cells discarded. if this bit is set to 1 by the t8208 logic, it indicates that cells with clp = 0 have been discarded for queue x. once this bit is set, it stays set until it is cleared by the customer (this bit is cleared automatically after a read operation if clear_on_read, bit 12 in regis- ter 0112h is set to 1). if this bit is 0, it indicates that cells with clp = 0 have not been discarded. reserved 00h 15:10 rw 0 reserved. program to 0. queuex_drop_cell_cnt[15:0] 02h 15:0 rw 0 queue x drop cell count[15:0]. the queuex_drop_cell_cnt[23:16] and queuex_drop_cell_cnt[15:0] fields together are a free-running counter of cells dropped on queue x of the sdram or tx utopia cell buffer.
agere systems inc. 195 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 179. queue x dropped cell count (qxdcc) (3000h to 31feh) (continued) name offset bit pos. type reset description the letter x in the data structure name and in the bit names represents the values of 0 through 127 for the 128 queues shown below. structure name base address structure name base address queue 0 base address (3000h) queue 32 base address (3080h) queue 1 base address (3004h) queue 33 base address (3084h) queue 2 base address (3008h) queue 34 base address (3088h) queue 3 base address (300ch) queue 35 base address (308ch) queue 4 base address (3010h) queue 36 base address (3090h) queue 5 base address (3014h) queue 37 base address (3094h) queue 6 base address (3018h) queue 38 base address (3098h) queue 7 base address (301ch) queue 39 base address (309ch) queue 8 base address (3020h) queue 40 base address (30a0h) queue 9 base address (3024h) queue 41 base address (30a4h) queue 10 base address (3028h) queue 42 base address (30a8h) queue 11 base address (302ch) queue 43 base address (30ach) queue 12 base address (3030h) queue 44 base address (30b0h) queue 13 base address (3034h) queue 45 base address (30b4h) queue 14 base address (3038h) queue 46 base address (30b8h) queue 15 base address (303ch) queue 47 base address (30bch) queue 16 base address (3040h) queue 48 base address (30c0h) queue 17 base address (3044h) queue 49 base address (30c4h) queue 18 base address (3048h) queue 50 base address (30c8h) queue 19 base address (304ch) queue 51 base address (30cch) queue 20 base address (3050h) queue 52 base address (30d0h) queue 21 base address (3054h) queue 53 base address (30d4h) queue 22 base address (3058h) queue 54 base address (30d8h) queue 23 base address (305ch) queue 55 base address (30dch) queue 24 base address (3060h) queue 56 base address (30e0h) queue 25 base address (3064h) queue 57 base address (30e4h) queue 26 base address (3068h) queue 58 base address (30e8h) queue 27 base address (306ch) queue 59 base address (30ech) queue 28 base address (3070h) queue 60 base address (30f0h) queue 29 base address (3074h) queue 61 base address (30f4h) queue 30 base address (3078h) queue 62 base address (30f8h) queue 31 base address (307ch) queue 63 base address (30fch)
196 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) table 179. queue x dropped cell count (qxdcc) (3000h to 31feh) (continued) name offset bit pos. type reset description the letter x in the data structure name and in the bit names represents the values of 0 through 127 for the 128 queues shown below. structure name base address structure name base address queue 64 base address (3100h) queue 96 base address (3180h) queue 65 base address (3104h) queue 97 base address (3184h) queue 66 base address (3108h) queue 98 base address (3188h) queue 67 base address (310ch) queue 99 base address (318ch) queue 68 base address (3110h) queue 100 base address (3190h) queue 69 base address (3114h) queue 101 base address (3194h) queue 70 base address (3118h) queue 102 base address (3198h) queue 71 base address (311ch) queue 103 base address (319ch) queue 72 base address (3120h) queue 104 base address (31a0h) queue 73 base address (3124h) queue 105 base address (31a4h) queue 74 base address (3128h) queue 106 base address (31a8h) queue 75 base address (312ch) queue 107 base address (31ach) queue 76 base address (3130h) queue 108 base address (31b0h) queue 77 base address (3134h) queue 109 base address (31b4h) queue 78 base address (3138h) queue 110 base address (31b8h) queue 79 base address (313ch) queue 111 base address (31bch) queue 80 base address (3140h) queue 112 base address (31c0h) queue 81 base address (3144h) queue 113 base address (31c4h) queue 82 base address (3148h) queue 114 base address (31c8h) queue 83 base address (314ch) queue 115 base address (31cch) queue 84 base address (3150h) queue 116 base address (31d0h) queue 85 base address (3154h) queue 117 base address (31d4h) queue 86 base address (3158h) queue 118 base address (31d8h) queue 87 base address (315ch) queue 119 base address (31dch) queue 88 base address (3160h) queue 120 base address (31e0h) queue 89 base address (3164h) queue 121 base address (31e4h) queue 90 base address (3168h) queue 122 base address (31e8h) queue 91 base address (316ch) queue 123 base address (31ech) queue 92 base address (3170h) queue 124 base address (31f0h) queue 93 base address (3174h) queue 125 base address (31f4h) queue 94 base address (3178h) queue 126 base address (31f8h) queue 95 base address (317ch) queue 127 base address (31fch)
agere systems inc. 197 advance data sheet september 2001 atm interconnect celxpres t8208 14 registers (continued) 14.3.6 external memories 14.3.6.1 look-up translation memory table 180. translation ram memory (tram) (100000h to 17fffeh) 14.3.6.2 sdram buffer memory table 181. sdram (sdram) (2000000h to 3fffffeh) name offset type reset description word0 00h rw x this memory space is used to access the translation ram memory. . . . . . . word3ffff 7fffeh name offset type reset description word0 00h rw x this memory space is used to access the sdram memory. . . . . . . wordfffffe 1fffffeh
198 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 15 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 182. maximum rating parameters and values 1. except for 5 v tolerant buffers where v ihmax = 5.5 v + 0.3 v. 2. maximum power dissipation may be determined from the following equation: p d = (125 c C t a )/22.5 c/w. 16 recommended operating conditions table 183. recommended operating conditions 17 handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. agere employs a human-body model (hbm) and a charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used to define the model. no industry-wide standard has been adopted for the cdm. a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely accepted and can be used for comparison. the hbm esd threshold presented here was obtained by using these circuit parameters. table 184. hbm esd threshold parameter symbol min typ max unit dc supply voltage with respect to ground v dd 4.2v input voltage range 1 v i1 v ss C 0.3 v dd + 0.3 v junction temperature range t j C40 125 c storage temperature t stg C60 160 c maximum power dissipation (package limit) 2 p d 2.44 w parameter symbol min typ max unit dc supply voltage with respect to ground v dd 3.0 3.6 v ambient operating temperature range t a C40 85 c device voltage (v) t8208 2000
agere systems inc. 199 advance data sheet september 2001 atm interconnect celxpres t8208 18 electrical requirements and characteristics 18.1 crystal information the celxpres t8208 device requires a crystal or external clock source. the crystal may have a frequency from 5 mhz to 40 mhz and is connected between xtalin and xtalout. external 5% capacitors must be connected from xtalin and xtalout to v ss . the value of the external capacitors is determined from the crystal data sheet using the crystal specification requirements shown below. table 185. crystal specifications the xtalin input may be driven by an external clock instead of a crystal. the frequency of the external source may be 5 mhz to 50 mhz. the external clock must meet the requirements shown below. table 186. external clock requirements the frequency of the t8208s main clock (mclk) is derived from the clock at the xtalin input (pclk). see section 5, pll configuration, for more information on these clocks. parameter value frequency 5 mhz to 40 mhz. oscillation mode fundamental parallel resonant. effective series resistance see figure 19 below. frequency tolerance and stability 5%. figure 18. crystal figure 19. negative resistance plot parameter min max frequency 5 mhz 50 mhz maximum rise or fall time 5 ns duty cycle 40% 60% crystal xtalin xtalout c 1 c 2 0 10 20 30 40 50 60 ?1000 ?800 ?600 ?400 ?200 0 frequency ( mhz ) negative resistance (ohms) 10p 20p 50p frequency (mhz) 50 pf 20 pf 10 pf negative resistance ( w ) = c1 = c2 = c1 = c2 = c1 = c2
200 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 18 electrical requirements and characteristics (continued) 18.2 dc electrical characteristics the following conditions apply except where noted: t a = C40 c to +85 c, v dd = 3.3 v 10%, 15 pf each output. table 187. dc electrical characteristics * this is the power consumed by the device under the following conditions: v dd = 3.3 v, pclk = 20 mhz, mclk = 100 mhz, utopia clock = 20 mhz, cell bus clock = 30 mhz, nominal slew rate (register 2eh). parameter symbol test conditions min typ max unit supply current i dd ma input voltage (ttl): low high v il v ih 2.0 0.8 v v input voltage (ttl 5 v tolerant): low high v il v ih 2.0 0.8 5.5 v v input voltage (gtl+): low high v il v ih 1.2 0.8 v v input voltage (xtalin): low high v il v ih 0.7 v dd 0.2 v dd v v output voltage (ttl 4 ma): low high v ol v oh i ol = 4 ma i oh = C4 ma 2.4 0.4 v v output voltage (ttl 6 ma): low high v ol v oh i ol = 6 ma i oh = C6 ma 2.4 0.4 v v output voltage (ttl 7 ma): low high v ol v oh i ol = 7 ma i oh = C7 ma 2.4 0.4 v v output voltage (ttl 10 ma): low high v ol v oh i ol = 10 ma i oh = C10 ma 2.4 0.4 v v output current (gtl+) i ol 6575ma output voltage (gtl+) v ol 0.30.5v input leakage current (ttl) 1 m a input leakage current (ttl with pull-ups) v il = v ss 67 m a input leakage current (cb_vref) 40 m a power dissipation p d 1.5*w
agere systems inc. 201 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements the following section describes the timing requirements. capacitve loading is in the range of 10 pf to 50 pf, unless otherwise specified. some timing requirements are dependent on the frequency of pclk or mclk. the terms mclkp and pclkp refer to the period of their respective clocks in ns when used in the following tables. table 188. input clocks note: the cell bus write clock (cb_wc*) should be delayed 1.5 ns to 4 ns relative to the cell bus read clock (cb_rc*) to ensure sufficient data hold time. table 189. output clocks clock name frequency (max) voltage level rise time (max) fall time (max) pulse width (min) high low high low cb_wc* 66 mhz 6.06 ns 6.06 ns cb_rc* 66 mhz 6.06 ns 6.06 ns u_rxclk 50 mhz 2.0 v 0.8 v 4.0 ns 4.0 ns 8.0 ns 8.0 ns u_txclk 50 mhz 2.0 v 0.8 v 4.0 ns 4.0 ns 8.0 ns 8.0 ns clock name frequency (max) rise time (max) fall time (max) pulse width (min) load high low sd_clk 100 mhz 1.0 ns 1.0 ns 4.0 ns 4.0 ns 15 pf u_rxclk 50 mhz 2.0 ns 2.0 ns 8.0 ns 8.0 ns 40 pf u_txclk 50 mhz 2.0 ns 2.0 ns 8.0 ns 8.0 ns 40 pf cb_gen_wc* 66 mhz 1.5 ns 1.5 ns 6.0 ns 6.0 ns cb_gen_rc* 66 mhz 1.5 ns 1.5 ns 6.0 ns 6.0 ns
202 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 19.1 microprocessor interface timing for access time information, see section 6.3.2, celxpres t8208 access performance. 5-7787bf 1. write_access_active is the logical or function of sel* and wr*_ds*. 2. load is 15 pf. note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active sig nal. figure 20. nonmultiplexed intel mode write access timing 5-7788bf 1. read_access_active is the logical or function of sel* and rd*_wr*. 2. load is 15 pf. note: sel* and rd*_wr* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active sign als. figure 21. nonmultiplexed intel mode read access timing write_access_active 1 a[7:0] d[7:0] rdy_dtack* 2 t1 t3 t6 t4 t2 t5 t7 read_access_active 1 a[7:0] d[7:0] rdy_dtack* 2 t1 t3 t6 t4 t2 t5 t8 t7 t9
agere systems inc. 203 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) table 190. nonmultiplexed intel mode write access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. table 191. nonmultiplexed intel mode read access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. symbol parameter min typ max unit t1 write_access_active falling edge to a[7:0] and d[7:0] valid 2 x pclkp C 4 ns t2 rdy_dtack* rising edge to write_access_active rising edge 0 ns t3 rdy_dtack* rising edge to a[7:0] and d[7:0] invalid 0 ns t4 write_access_active falling edge to rdy_dtack* falling edge 0 12 ns t5 rdy_dtack* low pulse width 1 t6 write_access_active rising edge to rdy_dtack* 3_state 0 5 ns t7 write_access_active rising edge to write_access_active fall- ing edge 25 ns symbol parameter min typ max unit t1 read_access_active falling edge to a[7:0] 2 x pclkp C 4 ns t2 rdy_dtack* rising edge to read_access_active rising edge 0ns t3 rdy_dtack* rising edge to a[7:0] invalid 0 ns t4 read_access_active falling edge to rdy_dtack* falling edge 012ns t5 rdy_dtack* low pulse width 1 t6 read_access_active rising edge to d[7:0] invalid 0 5 ns t7 d[7:0] valid to rdy_dtack* rising edge pclkp C 4 ns t8 read_access_active falling edge to d[7:0] drive 3 x pclkp C 4 ns t9 read_access_active rising edge to read_access_active falling edge 25 ns
204 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 5-7789bf 1. write_access_active is the logical or function of sel*, wr*_ds*, and rd*_wr*. 2. load is 50 pf. notes: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the write_access_active signals. figure 22. motorola mode write access timing 5-7790bf 1. read_access_active is the logical or function of sel*, wr*_ds*, and rd*_wr* . 2. load is 50 pf. notes: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the read_access_active signal. rd*_wr* must be stable any time both sel* and wr*_ds* are low to prevent glitches on the read_access_active signals. figure 23. motorola mode read access timing write_access_active 1 a[7:0] d[7:0] rdy_dtack* 2 t1 t3 t4 t2 t5 t7 t6 t8 read_access_active 1 a[7:0] d[7:0] rdy_dtack* 2 t1 t3 t4 t2 t5 t7 t6 t10 t8 t9 t11
agere systems inc. 205 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) table 192. motorola mode write access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. table 193. motorola mode read access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. symbol parameter min typ max unit t1 write_access_active falling edge to a[7:0] and d[7:0] valid 2 x pclkp C 4 ns t2 rdy_dtack* falling edge to write_access_active rising edge 0ns t3 rdy_dtack* falling edge to a[7:0] and d[7:0] invalid 0 ns t4 write_access_active falling edge to rdy_dtack* drive 0 12 ns t5 write_access_active falling edge to rdy_dtack* falling edge 1 t6 write_access_active rising edge to rdy_dtack* rising edge 0 5 ns t7 rdy_dtack* rising edge to rdy_dtack* 3-state 1 5 ns t8 write_access_active rising edge to write_access_active falling edge 25 ns symbol parameter min typ max unit t1 read_access_active falling edge to a[7:0] valid 2 x pclkp C 4 ns t2 rdy_dtack* falling edge to read_access_active rising edge 0ns t3 rdy_dtack* falling edge to a[7:0] invalid 0 ns t4 read_access_active falling edge to rdy_dtack* drive 0 12 ns t5 read_access_active falling edge to rdy_dtack* falling edge 1 t6 read_access_active rising edge to rdy_dtack* rising edge 05ns t7 rdy_dtack* rising edge to rdy_dtack* 3-state 1 5 ns t8 d[7:0] valid to rdy_dtack* falling edge pclkp C 4 ns t9 read_access_active rising edge to d[7:0] invalid 0 5 ns t10 read_access_active falling edge to d[7:0] drive 3 x pclkp C 4 ns t11 read_access_active rising edge to read_access_active falling edge 25 ns
206 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 5-7791bf 1. write_access_active is the logical or function of sel* and wr*_ds*. 2. load is 50 pf. note: sel* and wr*_ds* must not have coinciding edges in opposite directions to prevent glitches on the write_access_active sig nal. figure 24. multiplexed intel mode write access timing 5-7792bf 1. read_access_active is the logical or function of sel* and rd*_wr*. 2. load is 50 pf. note: sel* and rd*_wr* must not have coinciding edges in opposite directions prevent glitches on the read_access_active signals . figure 25. multiplexed intel mode read access timing write_access_active 1 a[0]/ale d[7:0] rdy_dtack* 2 t2 t6 t9 t7 t5 t8 t10 t3 t4 t1 t11 read_access_active 1 a[0]/ale d[7:0] rdy_dtack* 2 t2 t6 t9 t7 t5 t8 t10 t3 t4 t1 t11 t12
agere systems inc. 207 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) table 194. multiplexed intel mode write access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. table 195. multiplexed intel mode read access timing 1. see access times in table 11. note: the term pclkp in the table represents the period of pclk in ns. symbol parameter min typ max unit t1 a[0]/ale high pulse width 5 ns t2 write_access_active falling edge to a[0]/ale falling edge 2 x pclkp C 4 ns t3 d[7:0] valid to a[0]/ale falling edge 5 ns t4 a[0]/ale falling edge to d[7:0] invalid 0 ns t5 rdy_dtack* rising edge to write_access_active rising edge 0 ns t6 rdy_dtack* rising edge to d[7:0] invalid and a[0]/ale ris- ing edge 0 ns t7 write_access_active falling edge to rdy_dtack* falling edge 0 12 ns t8 rdy_dtack* low pulse width 1 t9 write_access_active rising edge to rdy_dtack* 3-state 0 5 ns t10 write_access_active falling edge to d[7:0] valid 2 x pclkp C 4 ns t11 write_access_active rising edge to write_access_active falling edge 25 ns symbol parameter min typ max unit t1 a[0]/ale high pulse width 5 ns t2 read_access_active falling edge to a[0]/ale falling edge 2 x pclkp C 4 ns t3 d[7:0] valid to a[0]/ale falling edge 5 ns t4 a[0]/ale falling edge to d[7:0] invalid 0 ns t5 rdy_dtack* rising edge to read_access_active rising edge 0ns t6 rdy_dtack* rising edge to a[0]/ale rising edge 0 ns t7 read_access_active falling edge to rdy_dtack* falling edge 012ns t8 rdy_dtack* low pulse width 1 t9 read_access_active rising edge to d[7:0] invalid and rdy_dtack* 3-state 05ns t10 read_access_active falling edge to d[7:0] drive 3 x pclkp C 4 ns t11 d[7:0] valid to rdy_dtack* rising edge pclkp C 4 ns t12 read_access_active rising edge to read_access_active falling edge 25 ns
208 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 19.2 utopia timing table 196. tx utopia timing (70 pf load on outputs) table 197. rx utopia timing (70 pf load on outputs) parameter min typ max unit u_txclk frequency 0 50mhz u_txclk duty cycle 40 60 % output delay from u_txclk, applies to the following signals: u_txaddr[4:0] u_txdata[15:0], u_txsoc, u_txprty, u_txenb*[3:0] u_txclav[0], u_shr_grant[1:0], u_shr_req[3:0] 1 1 1 1 10.6 10 7.66 12.6 ns ns ns ns input setup time to u_txclk, applies to the following signals: u_shr_req[3:0], u_shr_grant[1:0], u_txclav[3:0], u_txenb*[0], u_txaddr[4:0] 4 ns input hold time from u_txclk, applies to the following signals: u_shr_req[3:0], u_shr_grant[1:0], u_txclav[3:0], u_txenb*[0], u_txaddr[4:0] 1 ns parameter min typ max unit u_rxclk frequency 0 50 mhz u_rxclk duty cycle 40 60 % output delay from u_rxclk, applies to the following signals: u_rxaddr[4:0], u_rxenb*[3:0], u_rxclav[0] 1 1 1 9.01 8.36 7.19 ns ns ns input setup time to u_rxclk, applies to the following signals: u_rxenb*[3:0], u_rxclav[3:0], u_rxdata[15:0], u_rxparity, u_rxsoc, u_rxaddr[4:0] 4 ns input hold time from u_rxclk, applies to the following signals: u_rxenb*[3:0], u_rxclav[3:0], u_rxdata[15:0], u_rxprty, u_rxsoc, u_rxaddr[4:0] 1 ns
agere systems inc. 209 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 19.3 external lut memory timing 5-7795cf note: 30 pf load on outputs. 1. tr_rd_active is the logical or function of tr_cs*[1:0] and tr_we*. 2. when a single sram of 512k bytes is used (bit 5 in register 100h must be set to 1 ), tr_cs0 is used as tr_a[18]. figure 26. external lut memory read timing (cyc_per_acc = 2 and cyc_per_acc = 3) 5-7796af note: 30 pf load on outputs. 1. tr_wr_active is the logical or function of tr_cs*[1:0] and tr_we*. 2. when a single sram of 512k bytes is used (bit 5 in register 100h must be set to 1 ), tr_cs0 is used as tr_a[18]. figure 27. external lut memory write timing (cyc_per_acc = 2 and cyc_per_acc = 3) tr_a[18:0] tr_rd_active 1 tr_oe* tr_d[7:0] t1 t2 t3 t4 tr_a[18:0] tr_wr_active 1 tr_oe* tr_d[7:0] t2 t6 t4 t5 t7 t1 t3 t3
210 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) the term mclkp in tables 198, 199, 200, and 201, represents the period of mclk in ns. table 198. external lut memory read timing (cyc_per_acc = 2) table 199. external lut memory read timing (cyc_per_acc = 3) table 200. external lut memory write timing (cyc_per_acc = 2) table 201. external lut memory write timing (cyc_per_acc = 3) symbol parameter min typ max unit t1 tr_oe* low to tr_d[7:0] driven by sram chip 0 2 x mclkp C 11 ns t2 tr_a[17:0] & tr_cs*[1:0] valid to tr_d[7:0] valid 0 2 x mclkp C 11 ns t3 tr_oe* high to tr_d[7:0] invalid 0 ns t4 tr_oe* high to tr_d[7:0] 3-state mclkp ns symbol parameter min typ max unit t1 tr_oe* low to tr_d[7:0] driven by sram chip 0 3 x mclkp C 11 ns t2 tr_a[17:0] & tr_cs*[1:0] valid to tr_d[7:0] valid 0 3 x mclkp C 11 ns t3 tr_oe* high to tr_d[7:0] invalid 0 ns t4 tr_oe* high to tr_d[7:0] 3-state mclkp ns symbol parameter min typ max unit t1 tr_oe* high to tr_d[7:0] driven mclkp C 4 ns t2 tr_a[17:0] setup to tr_we* falling edge 2 ns t3 tr_we* low pulse width mclkp C 1 ns t4 tr_d[7:0] setup to tr_we* rising edge mclkp ns t5 tr_d[7:0] hold from tr_we* rising edge 2 ns t6 tr_a[17:0] hold from tr_we* rising edge 2 ns t7 tr_d[7:0] 3-state to tr_oe* low 0 ns symbol parameter min typ max unit t1 tr_oe* high to tr_d[7:0] driven mclkp C 4 ns t2 tr_a[17:0] setup to tr_we* falling edge 2 ns t3 tr_we* low pulse width 2 x mclkp C 1 ns t4 tr_d[7:0] setup to tr_we* rising edge 2 x mclkp ns t5 tr_d[7:0] hold from tr_we* rising edge 2 ns t6 tr_a[17:0] hold from tr_we* rising edge 2 ns t7 tr_d[7:0] 3-state to tr_oe* low 0 ns
agere systems inc. 211 advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 19.4 cell bus timing 5-7797bf 1. 25 pf load. figure 28. cell bus timing table 202. cell bus timing 1. pin loading = 25 pf. symbol parameter min typ max unit t1 cb_rc* falling edge to cb_wc* falling edge 1.5 4.0ns t2 cb_wc* falling edge to output valid 1 11.5ns t3 input setup to cb_rc* falling edge 1.0 ns t4 input hold from cb_rc* falling edge 2.0 ns t5 cb_wc* falling edge to output invalid 1 3.0 ns cb_rc* cb_wc* cb_d*[31:0], cb_ack* 1 , cb_fs* (output) cb_d*[31:0], cb_ack*, cb_fs* (input) t1 t5 t2 t4 t3
212 agere systems inc. advance data sheet september 2001 atm interconnect celxpres t8208 19 timing requirements (continued) 19.5 sdram interface timing 5-7798bf note: 15 pf load on outputs. figure 29. sdram interface timing table 203. sdram interface timing symbol parameter min typ max unit t1 sd_clk rising to outputs valid 7ns t2 sd_clk rising to outputs invalid 1.5 ns t3 sd_d[15:0] input setup to sd_clk rising edge 3 ns t4 sd_d[15:0] input hold from sd_clk rising edge 0 ns sd_clk* sd_ras* sd_cas* sd_we* sd_bs[1:0] sd_a[11:0] sd_d[15:0] sd_d[15:0] (sourced by t8208) (sampled by t8208) t4 t3 t1 t2
agere systems inc. 213 advance data sheet september 2001 atm interconnect celxpres t8208 20 outline diagram all dimensions shown are in millimeters. 5-4406.c 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 27.00 0.20 27.00 0.20 24.00 +0.70 C0.00 24.00 +0.70 C0.00 a1 ball identifier zone a b c d e f g h j k l m y n p r t u v w 12345678910 11 12 13 14 15 16 17 18 20 19 center array for thermal enhancement 19 spaces @ 1.27 = 24.13 a1 ball corner 19 spaces @ 1.27 = 24.13 0.75 0.15
advance data sheet september 2001 atm interconnect celxpres t8208 agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. celxpres is a trademark of agere systems inc. copyright ? 2001 agere systems inc. all rights reserved september 2001 ds01-295dlc (replaces ds01-071dlc) for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 21 ordering information part number package comcode t-8208---bal-db 272-pin pbgam, dry pack tray 108888876 t-8208---bal-dt 272-pin pbgam dry-bagged, tape & reel 700001513 motorola is a registered trademark of motorola, inc. intel is a registered trademark of intel corporation. transwitch and cellbus are registered trademarks of transwitch corp.

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